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Searched refs:post_div (Results 1 – 25 of 37) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pll.c83 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in amdgpu_pll_get_fb_ref_div() argument
88 ref_div_max = min(128 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div()
91 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in amdgpu_pll_get_fb_ref_div()
92 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
126 unsigned post_div_min, post_div_max, post_div; in amdgpu_pll_compute() local
154 post_div_min = pll->post_div; in amdgpu_pll_compute()
155 post_div_max = pll->post_div; in amdgpu_pll_compute()
199 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in amdgpu_pll_compute()
201 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, in amdgpu_pll_compute()
204 (ref_div * post_div)); in amdgpu_pll_compute()
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Datombios_crtc.c585 u32 post_div, in amdgpu_atombios_crtc_program_pll() argument
612 args.v1.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
622 args.v2.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
632 args.v3.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
649 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
679 args.v6.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
826 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
852 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
855 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
862 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
Damdgpu_atombios.h28 u32 post_div; member
68 u32 post_div; member
Datombios_crtc.h51 u32 post_div,
Damdgpu_atombios.c1038 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1058 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1076 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1090 dividers->post_div = args.v6_out.ucPllPostDiv; in amdgpu_atombios_get_clock_dividers()
1130 mpll_param->post_div = args.ucPostDiv; in amdgpu_atombios_get_memory_pll_dividers()
Damdgpu_mode.h197 uint32_t post_div; member
Dkv_dpm.c674 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
933 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
939 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
1001 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
1064 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1123 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
/Linux-v4.19/drivers/gpu/drm/radeon/
Dradeon_clocks.c39 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
54 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
55 if (post_div == 2) in radeon_legacy_get_engine_clock()
57 else if (post_div == 3) in radeon_legacy_get_engine_clock()
59 else if (post_div == 4) in radeon_legacy_get_engine_clock()
69 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
84 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
85 if (post_div == 2) in radeon_legacy_get_memory_clock()
87 else if (post_div == 3) in radeon_legacy_get_memory_clock()
89 else if (post_div == 4) in radeon_legacy_get_memory_clock()
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Dradeon_display.c916 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in avivo_get_fb_ref_div() argument
921 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); in avivo_get_fb_ref_div()
924 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in avivo_get_fb_ref_div()
925 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
959 unsigned post_div_min, post_div_max, post_div; in radeon_compute_pll_avivo() local
990 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
991 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
1035 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in radeon_compute_pll_avivo()
1037 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, in radeon_compute_pll_avivo()
1040 (ref_div * post_div)); in radeon_compute_pll_avivo()
[all …]
Dradeon_legacy_tv.c870 int post_div; in get_post_div() local
872 case 1: post_div = 0; break; in get_post_div()
873 case 2: post_div = 1; break; in get_post_div()
874 case 3: post_div = 4; break; in get_post_div()
875 case 4: post_div = 2; break; in get_post_div()
876 case 6: post_div = 6; break; in get_post_div()
877 case 8: post_div = 3; break; in get_post_div()
878 case 12: post_div = 7; break; in get_post_div()
880 default: post_div = 5; break; in get_post_div()
882 return post_div; in get_post_div()
Drv730_dpm.c65 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
66 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
81 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
82 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
143 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
144 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value()
156 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_mclk_value()
157 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_mclk_value()
Drv740_dpm.c144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
150 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
161 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
218 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
235 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
248 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
Dradeon_uvd.c922 unsigned post_div = vco_freq / target_freq; in radeon_uvd_calc_upll_post_div() local
925 if (post_div < pd_min) in radeon_uvd_calc_upll_post_div()
926 post_div = pd_min; in radeon_uvd_calc_upll_post_div()
929 if ((vco_freq / post_div) > target_freq) in radeon_uvd_calc_upll_post_div()
930 post_div += 1; in radeon_uvd_calc_upll_post_div()
933 if (post_div > pd_even && post_div % 2) in radeon_uvd_calc_upll_post_div()
934 post_div += 1; in radeon_uvd_calc_upll_post_div()
936 return post_div; in radeon_uvd_calc_upll_post_div()
Dradeon_legacy_crtc.c753 } *post_div, post_divs[] = { in radeon_set_pll() local
819 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
820 if (post_div->divider == post_divider) in radeon_set_pll()
824 if (!post_div->divider) in radeon_set_pll()
825 post_div = &post_divs[0]; in radeon_set_pll()
840 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
Drs780_dpm.c88 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
454 (min_dividers.post_div != max_dividers.post_div) || in rs780_set_engine_clock_scaling()
456 (max_dividers.post_div != current_max_dividers.post_div)) in rs780_set_engine_clock_scaling()
989 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_debugfs_print_current_performance_level() local
992 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level()
1011 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_get_current_sclk() local
1014 (post_div * ref_div); in rs780_dpm_get_current_sclk()
Datombios_crtc.c829 u32 post_div, in atombios_crtc_program_pll() argument
856 args.v1.ucPostDiv = post_div; in atombios_crtc_program_pll()
866 args.v2.ucPostDiv = post_div; in atombios_crtc_program_pll()
876 args.v3.ucPostDiv = post_div; in atombios_crtc_program_pll()
893 args.v5.ucPostDiv = post_div; in atombios_crtc_program_pll()
922 args.v6.ucPostDiv = post_div; in atombios_crtc_program_pll()
1069 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1096 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1101 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1104 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
[all …]
Dradeon_mode.h171 uint32_t post_div; member
580 u32 post_div; member
620 u32 post_div; member
Drv770_dpm.c333 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
422 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
452 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
514 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
528 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv770_populate_sclk_value()
529 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv770_populate_sclk_value()
Dkv_dpm.c545 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
848 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
854 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
916 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
979 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1038 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
/Linux-v4.19/drivers/clk/
Dclk-stm32f4.c1489 const struct stm32f4_pll_post_div_data *post_div; in stm32f4_rcc_init() local
1492 post_div = &post_div_data[n]; in stm32f4_rcc_init()
1494 hw = clk_register_pll_div(post_div->name, in stm32f4_rcc_init()
1495 post_div->parent, in stm32f4_rcc_init()
1496 post_div->flag, in stm32f4_rcc_init()
1497 base + post_div->offset, in stm32f4_rcc_init()
1498 post_div->shift, in stm32f4_rcc_init()
1499 post_div->width, in stm32f4_rcc_init()
1500 post_div->flag_div, in stm32f4_rcc_init()
1501 post_div->div_table, in stm32f4_rcc_init()
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/Linux-v4.19/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dmcp77.c55 u32 post_div = 0; in read_pll() local
61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
74 clock = clock / post_div; in read_pll()
/Linux-v4.19/drivers/video/fbdev/aty/
Dradeon_base.c1536 } *post_div, in radeon_calc_pll_regs() local
1605 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs()
1606 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1610 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs()
1619 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1620 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1621 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1629 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1630 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1631 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
[all …]
Dradeonfb.h233 int post_div; member
/Linux-v4.19/drivers/media/tuners/
Dtda18271-priv.h192 u32 *freq, u8 *post_div, u8 *div);
Dtda18271-maps.c1065 u32 *freq, u8 *post_div, u8 *div) in tda18271_lookup_pll_map() argument
1105 *post_div = map[i].pd; in tda18271_lookup_pll_map()
1109 i, map_name, *post_div, *div); in tda18271_lookup_pll_map()

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