Searched refs:pllclk (Results 1 – 6 of 6) sorted by relevance
127 unsigned int pllclk, ahbclk, apbclk, val; in nuc900_set_clkval() local129 pllclk = 0; in nuc900_set_clkval()135 pllclk = PLL_66MHZ; in nuc900_set_clkval()141 pllclk = PLL_100MHZ; in nuc900_set_clkval()147 pllclk = PLL_120MHZ; in nuc900_set_clkval()153 pllclk = PLL_166MHZ; in nuc900_set_clkval()159 pllclk = PLL_200MHZ; in nuc900_set_clkval()165 __raw_writel(pllclk, REG_PLLCON0); in nuc900_set_clkval()
39 u32 pllclk; in pic32_get_sysclk() local62 pllclk = plliclk ? FRC_CLK : PIC32_POSC_FREQ; in pic32_get_sysclk()80 osc_freq = ((pllclk / pllidiv) * pllmult) / pllodiv; in pic32_get_sysclk()
18 pllclk: pllclk {
24 pllclk: pllclk { label32 clocks = <&pllclk>;
25 pllclk: pllclk { label33 clocks = <&pllclk>;
75 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_is_enabled() local78 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()88 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_recalc_rate() local96 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()98 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()99 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()128 pllclk->version); in xgene_clk_pll_recalc_rate()
