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Searched refs:pll_value (Results 1 – 6 of 6) sorted by relevance

/Linux-v4.19/drivers/staging/sm750fb/
Dddk750_chip.h42 struct pll_value { struct
97 unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
98 unsigned int sm750_format_pll_reg(struct pll_value *pPLL);
Dddk750_chip.c58 struct pll_value pll; in set_chip_clock()
314 struct pll_value *pll) in sm750_calc_pll_value()
386 unsigned int sm750_format_pll_reg(struct pll_value *pPLL) in sm750_format_pll_reg()
Dddk750_mode.c78 struct pll_value *pll) in programModeRegisters()
211 struct pll_value pll; in ddk750_setModeTiming()
/Linux-v4.19/arch/m68k/q40/
Dconfig.c276 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
278 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
293 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | in q40_set_rtc_pll()
/Linux-v4.19/drivers/video/fbdev/geode/
Dvideo_cs5530.c29 u32 pll_value; member
80 value = cs5530_pll_table[0].pll_value; in cs5530_set_dclk_frequency()
88 value = cs5530_pll_table[i].pll_value; in cs5530_set_dclk_frequency()
/Linux-v4.19/include/uapi/linux/
Drtc.h58 int pll_value; /* get/set correction value */ member