Searched refs:pll_info (Results 1 – 15 of 15) sorted by relevance
84 const struct ingenic_cgu_pll_info *pll_info; in ingenic_pll_recalc_rate() local92 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()95 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()98 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()99 m += pll_info->m_offset; in ingenic_pll_recalc_rate()100 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()101 n += pll_info->n_offset; in ingenic_pll_recalc_rate()102 od_enc = ctl >> pll_info->od_shift; in ingenic_pll_recalc_rate()103 od_enc &= GENMASK(pll_info->od_bits - 1, 0); in ingenic_pll_recalc_rate()104 bypass = !pll_info->no_bypass_bit && in ingenic_pll_recalc_rate()[all …]
732 uint16_t pll_info; in radeon_combios_get_clock_info() local740 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); in radeon_combios_get_clock_info()741 if (pll_info) { in radeon_combios_get_clock_info()742 rev = RBIOS8(pll_info); in radeon_combios_get_clock_info()745 p1pll->reference_freq = RBIOS16(pll_info + 0xe); in radeon_combios_get_clock_info()746 p1pll->reference_div = RBIOS16(pll_info + 0x10); in radeon_combios_get_clock_info()747 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); in radeon_combios_get_clock_info()748 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); in radeon_combios_get_clock_info()753 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); in radeon_combios_get_clock_info()754 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); in radeon_combios_get_clock_info()[all …]
755 const struct audio_pll_info *pll_info, in get_azalia_clock_info_dp() argument770 pll_info->dp_dto_source_clock_in_khz * 10; in get_azalia_clock_info_dp()777 const struct audio_pll_info *pll_info) in dce_aud_wall_dto_setup() argument813 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; in dce_aud_wall_dto_setup()835 pll_info, in dce_aud_wall_dto_setup()
1206 calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency; in calc_pll_max_vco_construct()1208 fw_info.pll_info.min_output_pxl_clk_pll_frequency; in calc_pll_max_vco_construct()1210 fw_info.pll_info.max_output_pxl_clk_pll_frequency; in calc_pll_max_vco_construct()1217 fw_info.pll_info.max_input_pxl_clk_pll_frequency; in calc_pll_max_vco_construct()1224 fw_info.pll_info.min_input_pxl_clk_pll_frequency; in calc_pll_max_vco_construct()1343 clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency; in dce110_clk_src_construct()
146 const struct audio_pll_info *pll_info);
51 const struct audio_pll_info *pll_info);
99 struct audio_pll_info pll_info; member
159 struct pll_info { struct165 } pll_info; member
47 struct pll_info { struct138 struct pll_info pll_limits;
138 struct pll_info { struct342 struct pll_info pll;
692 info->pll_info.crystal_frequency = in get_firmware_info_v1_4()694 info->pll_info.min_input_pxl_clk_pll_frequency = in get_firmware_info_v1_4()696 info->pll_info.max_input_pxl_clk_pll_frequency = in get_firmware_info_v1_4()698 info->pll_info.min_output_pxl_clk_pll_frequency = in get_firmware_info_v1_4()700 info->pll_info.max_output_pxl_clk_pll_frequency = in get_firmware_info_v1_4()743 info->pll_info.crystal_frequency = in get_firmware_info_v2_1()745 info->pll_info.min_input_pxl_clk_pll_frequency = in get_firmware_info_v2_1()747 info->pll_info.max_input_pxl_clk_pll_frequency = in get_firmware_info_v2_1()749 info->pll_info.min_output_pxl_clk_pll_frequency = in get_firmware_info_v2_1()751 info->pll_info.max_output_pxl_clk_pll_frequency = in get_firmware_info_v2_1()[all …]
1397 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; in get_firmware_info_v3_1()1400 if (info->pll_info.crystal_frequency == 0) in get_firmware_info_v3_1()1401 info->pll_info.crystal_frequency = 27000; in get_firmware_info_v3_1()1470 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; in get_firmware_info_v3_2()1472 if (info->pll_info.crystal_frequency == 0) { in get_firmware_info_v3_2()1474 info->pll_info.crystal_frequency = 27000; in get_firmware_info_v3_2()1476 info->pll_info.crystal_frequency = 100000; in get_firmware_info_v3_2()
1194 audio_output->pll_info.dp_dto_source_clock_in_khz = in build_audio_output()1199 audio_output->pll_info.feed_back_divider = in build_audio_output()1202 audio_output->pll_info.dto_source = in build_audio_output()1207 audio_output->pll_info.ss_enabled = true; in build_audio_output()1209 audio_output->pll_info.ss_percentage = in build_audio_output()1975 &audio_output.pll_info); in dce110_setup_audio_dto()2003 &audio_output.pll_info); in dce110_setup_audio_dto()
333 return info.pll_info.crystal_frequency; in dal_i2caux_get_reference_clock()
155 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency; in dc_create_resource_pool()
