Searched refs:pll_con (Results 1 – 2 of 2) sorted by relevance
111 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local114 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()115 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; in samsung_pll2126_recalc_rate()116 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; in samsung_pll2126_recalc_rate()117 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; in samsung_pll2126_recalc_rate()144 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local147 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()148 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; in samsung_pll3000_recalc_rate()149 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; in samsung_pll3000_recalc_rate()150 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; in samsung_pll3000_recalc_rate()[all …]
299 u32 pll_con = readl(reg_base + reg); in exynos4_clk_enable_pll() local300 pll_con |= PLL_ENABLED; in exynos4_clk_enable_pll()301 writel(pll_con, reg_base + reg); in exynos4_clk_enable_pll()303 while (!(pll_con & PLL_LOCKED)) { in exynos4_clk_enable_pll()305 pll_con = readl(reg_base + reg); in exynos4_clk_enable_pll()311 u32 pll_con; in exynos4_clk_wait_for_pll() local313 pll_con = readl(reg_base + reg); in exynos4_clk_wait_for_pll()314 if (!(pll_con & PLL_ENABLED)) in exynos4_clk_wait_for_pll()317 while (!(pll_con & PLL_LOCKED)) { in exynos4_clk_wait_for_pll()319 pll_con = readl(reg_base + reg); in exynos4_clk_wait_for_pll()
