Searched refs:pll_28nm (Results 1 – 2 of 2) sorted by relevance
99 static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, in pll_28nm_poll_for_ready() argument106 val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); in pll_28nm_poll_for_ready()119 static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) in pll_28nm_software_reset() argument121 void __iomem *base = pll_28nm->mmio; in pll_28nm_software_reset()139 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_set_rate() local140 struct device *dev = &pll_28nm->pdev->dev; in dsi_pll_28nm_clk_set_rate()141 void __iomem *base = pll_28nm->mmio; in dsi_pll_28nm_clk_set_rate()232 if (pll_28nm->vco_delay) in dsi_pll_28nm_clk_set_rate()233 udelay(pll_28nm->vco_delay); in dsi_pll_28nm_clk_set_rate()254 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_is_enabled() local[all …]
94 static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, in pll_28nm_poll_for_ready() argument101 val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); in pll_28nm_poll_for_ready()121 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_set_rate() local122 void __iomem *base = pll_28nm->mmio; in dsi_pll_28nm_clk_set_rate()162 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_is_enabled() local164 return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, in dsi_pll_28nm_clk_is_enabled()172 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_recalc_rate() local173 void __iomem *base = pll_28nm->mmio; in dsi_pll_28nm_clk_recalc_rate()297 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_enable_seq() local298 struct device *dev = &pll_28nm->pdev->dev; in dsi_pll_28nm_enable_seq()[all …]
