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Searched refs:pll8 (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_dpll_mgr.h166 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, member
Dintel_dpll_mgr.c1513 temp |= pll->state.hw_state.pll8; in bxt_ddi_pll_enable()
1628 hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
1629 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; in bxt_ddi_pll_get_hw_state()
1779 dpll_hw_state->pll8 = targ_cnt; in bxt_ddi_set_dpll_hw_state()
1866 hw_state->pll8, in bxt_dump_hw_state()
Dintel_display.c11564 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); in intel_pipe_config_compare()
/Linux-v4.19/drivers/clk/qcom/
Dgcc-mdm9615.c86 static struct clk_pll pll8 = { variable
1600 [PLL8] = &pll8.clkr,
Dgcc-msm8960.c62 static struct clk_pll pll8 = { variable
2993 [PLL8] = &pll8.clkr,
3218 [PLL8] = &pll8.clkr,
Dgcc-msm8660.c35 static struct clk_pll pll8 = { variable
2457 [PLL8] = &pll8.clkr,
Dgcc-ipq806x.c89 static struct clk_pll pll8 = { variable
2687 [PLL8] = &pll8.clkr,