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Searched refs:pll3 (Results 1 – 18 of 18) sorted by relevance

/Linux-v4.19/arch/powerpc/boot/dts/fsl/
Dp4080si-post.dtsi386 pll3: pll3@860 { label
391 clock-output-names = "pll3", "pll3-div2";
416 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
417 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
425 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
426 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
434 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
435 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
443 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
444 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
Dt4240si-post.dtsi962 pll3: pll3@860 { label
967 clock-output-names = "pll3", "pll3-div2", "pll3-div4";
1008 clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
1010 clock-names = "pll3", "pll3-div2", "pll3-div4",
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
32 "pll3", "dsi0phy", "dsi1phy",
Drenesas,rcar-gen2-cpg-clocks.txt24 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
45 clock-output-names = "main", "pll0, "pll1", "pll3",
Dfixed-factor-clock.txt19 - allwinner,sun4i-a10-pll3-2x-clk
Dprima2-clock.txt19 pll3 4
Dsunxi.txt13 "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
/Linux-v4.19/drivers/clk/sunxi/
DMakefile16 obj-y += clk-sun4i-pll3.o
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_dpll_mgr.h166 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, member
Dintel_dpll_mgr.c1499 temp |= pll->state.hw_state.pll3; in bxt_ddi_pll_enable()
1620 hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
1621 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
1774 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
1864 hw_state->pll3, in bxt_dump_hw_state()
Dintel_ddi.c1641 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_calc_pll_link()
Dintel_display.c11562 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); in intel_pipe_config_compare()
/Linux-v4.19/drivers/clk/sirf/
Dclk-prima2.c61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
Dclk-atlas6.c62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
/Linux-v4.19/drivers/gpu/drm/tegra/
Dsor.c295 unsigned int pll3; member
1655 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1657 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_edp_enable()
2240 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2242 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2442 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2451 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2796 .pll3 = 0x1a,
2821 .pll3 = 0x1a,
2865 .pll3 = 0x166,
/Linux-v4.19/drivers/clk/qcom/
Dgcc-msm8960.c35 static struct clk_pll pll3 = { variable
2991 [PLL3] = &pll3.clkr,
3216 [PLL3] = &pll3.clkr,
Dgcc-ipq806x.c62 static struct clk_pll pll3 = { variable
2685 [PLL3] = &pll3.clkr,
/Linux-v4.19/arch/arm/boot/dts/
Dsh73a0.dtsi638 "pll3", "dsi0phy", "dsi1phy",