Searched refs:pll1_div (Results 1 – 3 of 3) sorted by relevance
29 static unsigned int pll1_div; variable46 unsigned long rate = clk->parent->rate / pll1_div; in pll_recalc()142 pll1_div = 3; in arch_clk_init()144 pll1_div = 4; in arch_clk_init()146 pll1_div = 1; in arch_clk_init()
40 u8 pll1_div; member
471 div = cpg_pll_config->pll1_div; in rcar_gen3_cpg_clk_register()
