| /Linux-v4.19/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll.c | 16 static int dsi_pll_enable(struct msm_dsi_pll *pll) in dsi_pll_enable() argument
24 if (unlikely(pll->pll_on)) in dsi_pll_enable()
28 for (i = 0; i < pll->en_seq_cnt; i++) { in dsi_pll_enable()
29 ret = pll->enable_seqs[i](pll); in dsi_pll_enable()
41 pll->pll_on = true; in dsi_pll_enable()
46 static void dsi_pll_disable(struct msm_dsi_pll *pll) in dsi_pll_disable() argument
48 if (unlikely(!pll->pll_on)) in dsi_pll_disable()
51 pll->disable_seq(pll); in dsi_pll_disable()
53 pll->pll_on = false; in dsi_pll_disable()
62 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in msm_dsi_pll_helper_clk_round_rate() local
[all …]
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| D | dsi_pll_14nm.c | 173 struct dsi_pll_14nm *pll; member
222 static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll) in dsi_pll_14nm_input_init() argument
224 pll->in.fref = pll->vco_ref_clk_rate; in dsi_pll_14nm_input_init()
225 pll->in.fdata = 0; in dsi_pll_14nm_input_init()
226 pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ in dsi_pll_14nm_input_init()
227 pll->in.ldo_en = 0; /* disabled for now */ in dsi_pll_14nm_input_init()
230 pll->in.refclk_dbler_en = 0; in dsi_pll_14nm_input_init()
231 pll->in.vco_measure_time = 5; in dsi_pll_14nm_input_init()
232 pll->in.kvco_measure_time = 5; in dsi_pll_14nm_input_init()
233 pll->in.bandgap_timer = 4; in dsi_pll_14nm_input_init()
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| /Linux-v4.19/drivers/clk/tegra/ |
| D | clk-pll.c | 287 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
291 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
294 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
297 val = pll_readl_misc(pll); in clk_pll_enable_lock()
298 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
299 pll_writel_misc(val, pll); in clk_pll_enable_lock()
302 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
308 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
309 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
313 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
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| /Linux-v4.19/drivers/clk/mediatek/ |
| D | clk-pll.c | 62 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
64 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
67 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
70 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
91 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, in mtk_pll_set_rate_regs() argument
97 pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; in mtk_pll_set_rate_regs()
100 val = readl(pll->pd_addr); in mtk_pll_set_rate_regs()
101 val &= ~(POSTDIV_MASK << pll->data->pd_shift); in mtk_pll_set_rate_regs()
102 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
105 if (pll->pd_addr != pll->pcw_addr) { in mtk_pll_set_rate_regs()
[all …]
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| /Linux-v4.19/drivers/clk/sprd/ |
| D | pll.c | 18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
28 ((pwidth(pll, member)) ? \
29 GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \
30 pshift(pll, member)) : 0)
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| /Linux-v4.19/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
120 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
127 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
128 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
130 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
136 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
142 if (pll->xres != 0) { in aty_dsp_gt()
[all …]
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| /Linux-v4.19/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 135 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
141 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
143 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
148 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
163 #define wait_for_pll_enable_active(pll) \ argument
164 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
166 #define wait_for_pll_enable_lock(pll) \ argument
167 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
169 #define wait_for_pll_disable(pll) \ argument
170 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
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| D | clk-pll.c | 34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
39 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
48 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
60 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
69 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
75 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
79 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
84 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
90 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
95 regmap_read(pll->clkr.regmap, pll->l_reg, &l); in clk_pll_recalc_rate()
[all …]
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| /Linux-v4.19/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 85 struct iproc_pll *pll; member
128 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) in pll_get_rate_index() argument
132 for (i = 0; i < pll->num_vco_entries; i++) in pll_get_rate_index()
133 if (target_rate == pll->vco_param[i].rate) in pll_get_rate_index()
136 if (i >= pll->num_vco_entries) in pll_get_rate_index()
157 static int pll_wait_for_lock(struct iproc_pll *pll) in pll_wait_for_lock() argument
160 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock()
163 u32 val = readl(pll->status_base + ctrl->status.offset); in pll_wait_for_lock()
173 static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, in iproc_pll_write() argument
176 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_write()
[all …]
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| D | clk-iproc-armpll.c | 76 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
81 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
90 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
94 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
116 static int __get_mdiv(struct iproc_arm_pll *pll) in __get_mdiv() argument
122 fid = __get_fid(pll); in __get_mdiv()
131 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); in __get_mdiv()
138 val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); in __get_mdiv()
151 static unsigned int __get_ndiv(struct iproc_arm_pll *pll) in __get_ndiv() argument
156 val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); in __get_ndiv()
[all …]
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| /Linux-v4.19/drivers/media/i2c/ |
| D | smiapp-pll.c | 61 static void print_pll(struct device *dev, struct smiapp_pll *pll) in print_pll() argument
63 dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); in print_pll()
64 dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); in print_pll()
65 if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { in print_pll()
66 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); in print_pll()
67 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); in print_pll()
69 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); in print_pll()
70 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); in print_pll()
72 dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); in print_pll()
73 dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); in print_pll()
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| D | aptina-pll.c | 26 struct aptina_pll *pll) in aptina_pll_calculate() argument
36 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
38 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
39 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
44 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
50 div = gcd(pll->pix_clock, pll->ext_clock); in aptina_pll_calculate()
51 pll->m = pll->pix_clock / div; in aptina_pll_calculate()
52 div = pll->ext_clock / div; in aptina_pll_calculate()
64 mf_min = DIV_ROUND_UP(limits->m_min, pll->m); in aptina_pll_calculate()
66 (pll->ext_clock / limits->n_min * pll->m)); in aptina_pll_calculate()
[all …]
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| /Linux-v4.19/drivers/clk/imx/ |
| D | clk-pllv3.c | 56 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
59 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
62 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) in clk_pllv3_wait_lock()
67 if (readl_relaxed(pll->base) & BM_PLL_LOCK) in clk_pllv3_wait_lock()
74 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; in clk_pllv3_wait_lock()
79 struct clk_pllv3 *pll = to_clk_pllv3(hw); in clk_pllv3_prepare() local
82 val = readl_relaxed(pll->base); in clk_pllv3_prepare()
83 if (pll->powerup_set) in clk_pllv3_prepare()
84 val |= pll->power_bit; in clk_pllv3_prepare()
86 val &= ~pll->power_bit; in clk_pllv3_prepare()
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| D | clk-pllv1.c | 32 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) in is_imx1_pllv1() argument
34 return pll->type == IMX_PLLV1_IMX1; in is_imx1_pllv1()
37 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) in is_imx21_pllv1() argument
39 return pll->type == IMX_PLLV1_IMX21; in is_imx21_pllv1()
42 static inline bool is_imx27_pllv1(struct clk_pllv1 *pll) in is_imx27_pllv1() argument
44 return pll->type == IMX_PLLV1_IMX27; in is_imx27_pllv1()
47 static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn) in mfn_is_negative() argument
49 return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN); in mfn_is_negative()
55 struct clk_pllv1 *pll = to_clk_pllv1(hw); in clk_pllv1_recalc_rate() local
62 reg = readl(pll->base); in clk_pllv1_recalc_rate()
[all …]
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| /Linux-v4.19/drivers/clk/meson/ |
| D | clk-pll.c | 46 struct meson_clk_pll_data *pll) in __pll_params_to_rate() argument
51 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { in __pll_params_to_rate()
55 (1 << pll->frac.width)); in __pll_params_to_rate()
65 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); in meson_clk_pll_recalc_rate() local
69 pllt.n = meson_parm_read(clk->map, &pll->n); in meson_clk_pll_recalc_rate()
70 pllt.m = meson_parm_read(clk->map, &pll->m); in meson_clk_pll_recalc_rate()
71 pllt.od = meson_parm_read(clk->map, &pll->od); in meson_clk_pll_recalc_rate()
73 pllt.od2 = MESON_PARM_APPLICABLE(&pll->od2) ? in meson_clk_pll_recalc_rate()
74 meson_parm_read(clk->map, &pll->od2) : in meson_clk_pll_recalc_rate()
77 pllt.od3 = MESON_PARM_APPLICABLE(&pll->od3) ? in meson_clk_pll_recalc_rate()
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| /Linux-v4.19/drivers/clk/rockchip/ |
| D | clk-pll.c | 59 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
61 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
64 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
75 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
76 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
80 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
94 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
96 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
101 ret = regmap_read(grf, pll->lock_offset, &val); in rockchip_pll_wait_lock()
108 if (val & BIT(pll->lock_shift)) in rockchip_pll_wait_lock()
[all …]
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| /Linux-v4.19/drivers/clk/pistachio/ |
| D | clk-pll.c | 81 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() argument
83 return readl(pll->base + reg); in pll_readl()
86 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
88 writel(val, pll->base + reg); in pll_writel()
91 static inline void pll_lock(struct pistachio_clk_pll *pll) in pll_lock() argument
93 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_lock()
110 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_get_mode() local
113 val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD; in pll_frac_get_mode()
119 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_set_mode() local
122 val = pll_readl(pll, PLL_CTRL3); in pll_frac_set_mode()
[all …]
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| /Linux-v4.19/drivers/clk/samsung/ |
| D | clk-pll.c | 38 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
40 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
43 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
54 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
55 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
59 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
70 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
73 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
74 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
75 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
[all …]
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| /Linux-v4.19/drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi_pll.c | 26 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
29 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
44 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_enable() local
45 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable()
48 r = pm_runtime_get_sync(&pll->pdev->dev); in hdmi_pll_enable()
62 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_disable() local
63 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable()
70 r = pm_runtime_put_sync(&pll->pdev->dev); in hdmi_pll_disable()
135 struct dss_pll *pll = &hpll->pll; in hdmi_init_pll_data() local
145 pll->name = "hdmi"; in hdmi_init_pll_data()
[all …]
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| D | video-pll.c | 26 struct dss_pll pll; member
62 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
64 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable()
67 r = dss_runtime_get(pll->dss); in dss_video_pll_enable()
71 dss_ctrl_pll_enable(pll, true); in dss_video_pll_enable()
75 r = dss_pll_wait_reset_done(pll); in dss_video_pll_enable()
85 dss_ctrl_pll_enable(pll, false); in dss_video_pll_enable()
86 dss_runtime_put(pll->dss); in dss_video_pll_enable()
91 static void dss_video_pll_disable(struct dss_pll *pll) in dss_video_pll_disable() argument
93 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_disable()
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| /Linux-v4.19/drivers/clk/mxs/ |
| D | clk-pll.c | 40 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
42 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
51 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare() local
53 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
58 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
60 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
67 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
69 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
75 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
77 return pll->rate; in clk_pll_recalc_rate()
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| /Linux-v4.19/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8996.c | 88 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
90 return platform_get_drvdata(pll->pdev); in pll_get_phy()
93 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
96 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
99 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
101 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
104 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
107 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
405 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); in hdmi_8996_pll_set_clk_rate() local
406 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_8996_pll_set_clk_rate()
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| /Linux-v4.19/drivers/clk/st/ |
| D | clkgen-pll.c | 186 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_locked() local
187 u32 locked = CLKGEN_READ(pll, locked_status); in clkgen_pll_is_locked()
194 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_enabled() local
195 u32 poweroff = CLKGEN_READ(pll, pdn_status); in clkgen_pll_is_enabled()
201 struct clkgen_pll *pll = to_clkgen_pll(hw); in __clkgen_pll_enable() local
202 void __iomem *base = pll->regs_base; in __clkgen_pll_enable()
203 struct clkgen_field *field = &pll->data->locked_status; in __clkgen_pll_enable()
210 CLKGEN_WRITE(pll, pdn_ctrl, 0); in __clkgen_pll_enable()
216 if (pll->data->switch2pll_en) in __clkgen_pll_enable()
217 CLKGEN_WRITE(pll, switch2pll, 0); in __clkgen_pll_enable()
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| /Linux-v4.19/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_pll.c | 26 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
29 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
42 void hdmi_pll_compute(struct hdmi_pll_data *pll, in hdmi_pll_compute() argument
50 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
52 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
104 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_enable() local
105 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable()
119 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_disable() local
120 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable()
182 struct dss_pll *pll = &hpll->pll; in dsi_init_pll_data() local
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| D | video-pll.c | 26 struct dss_pll pll; member
62 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
64 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable()
71 dss_ctrl_pll_enable(pll->id, true); in dss_video_pll_enable()
75 r = dss_pll_wait_reset_done(pll); in dss_video_pll_enable()
85 dss_ctrl_pll_enable(pll->id, false); in dss_video_pll_enable()
91 static void dss_video_pll_disable(struct dss_pll *pll) in dss_video_pll_disable() argument
93 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_disable()
99 dss_ctrl_pll_enable(pll->id, false); in dss_video_pll_disable()
142 struct dss_pll *pll; in dss_video_pll_init() local
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