| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 647 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
687 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
733 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
736 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
758 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
761 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
768 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
781 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
906 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_commit_state_no_check()
1001 for (i = 0; i < dc->res_pool->pipe_count; i++) in dc_post_update_surfaces_to_stream()
[all …]
|
| D | dc_debug.c | 320 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
333 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
|
| D | dc_surface.c | 118 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
|
| D | dc_resource.c | 225 for (i = 0; i < pool->pipe_count && i < num_audio; i++) { in resource_construct()
1161 for (i = pool->pipe_count - 1; i >= 0; i--) { in find_idle_secondary_pipe()
1235 for (i = pool->pipe_count - 1; i >= 0; i--) { in acquire_free_pipe_for_stream()
1262 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_split_pipe()
1384 for (i = pool->pipe_count - 1; i >= 0; i--) { in dc_remove_plane_from_context()
1636 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_free_pipe()
2011 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dc_validate_global_state()
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 124 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
156 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
181 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
213 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
245 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
284 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
561 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
588 for (i = 0; i < dc->res_pool->pipe_count; i++) { in bios_golden_init()
608 for (i = 0; i < dc->res_pool->pipe_count; i++) { in false_optc_underflow_wa()
741 for (i = 0; i < dc->res_pool->pipe_count; i++) in reset_back_end_for_pipe()
[all …]
|
| D | dcn10_resource.c | 839 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
1121 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1249 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1309 pool->base.pipe_count = j; in construct()
1315 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in construct()
1316 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in construct()
1338 dc->caps.max_planes = pool->base.pipe_count; in construct()
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 668 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
821 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1069 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1070 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1071 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1072 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1073 pool->pipe_count++; in underlay_create()
1168 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1169 pool->base.underlay_pipe_index = pool->base.pipe_count; in construct()
1258 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
[all …]
|
| D | dce110_hw_sequencer.c | 1529 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vga_and_power_gate_all_controllers()
1819 for (i = 0; i < dc->res_pool->pipe_count; i++) { in should_enable_fbc()
1954 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
1981 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
1982 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2030 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2055 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2348 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2379 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2719 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_for_surface()
[all …]
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 672 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
810 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
902 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
948 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1003 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1096 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1134 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1189 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1278 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
1316 dc->caps.max_planes = pool->base.pipe_count; in dce83_construct()
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 639 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
719 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
916 pool->base.pipe_count = res_cap.num_timing_generator; in construct()
923 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
975 dc->caps.max_planes = pool->base.pipe_count; in construct()
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 478 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
878 pool->base.pipe_count = res_cap.num_timing_generator; in construct()
971 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1036 pool->base.pipe_count = j; in construct()
1047 dc->caps.max_planes = pool->base.pipe_count; in construct()
|
| /Linux-v4.19/sound/pci/mixart/ |
| D | mixart_core.h | 245 u32 pipe_count; /* set to 1 for instance */ member
407 u32 pipe_count; /* set to 1 (array size !) */ member
|
| D | mixart.c | 114 group_state.pipe_count = 1; in mixart_set_pipe_state()
137 group_state.pipe_count = 0; /* in case of start same command once again with pipe_count=0 */ in mixart_set_pipe_state()
580 stream_param.pipe_count = 1; /* set to 1 */ in mixart_set_format()
|
| /Linux-v4.19/kernel/rcu/ |
| D | rcutorture.c | 1313 int pipe_count; in rcu_torture_one_read() local
1335 pipe_count = p->rtort_pipe_count; in rcu_torture_one_read()
1336 if (pipe_count > RCU_TORTURE_PIPE_LEN) { in rcu_torture_one_read()
1338 pipe_count = RCU_TORTURE_PIPE_LEN; in rcu_torture_one_read()
1341 if (pipe_count > 1) { in rcu_torture_one_read()
1346 __this_cpu_inc(rcu_torture_count[pipe_count]); in rcu_torture_one_read()
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 657 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
773 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
1101 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1203 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1261 dc->caps.max_planes = pool->base.pipe_count; in construct()
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 148 unsigned int pipe_count; member
|
| D | dce_calcs.h | 485 int pipe_count,
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clocks.c | 545 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn1_ramp_up_dispclk_with_dpp()
|
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 829 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { in dcn_validate_bandwidth()
1081 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { in dcn_validate_bandwidth()
|
| D | dce_calcs.c | 2757 const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data) in populate_initial_data() argument
2773 for (i = 0; i < pipe_count; i++) { in populate_initial_data()
2883 for (i = 0; i < pipe_count; i++) { in populate_initial_data()
2985 int pipe_count, in bw_calcs() argument
2993 populate_initial_data(pipe, pipe_count, data); in bw_calcs()
|
