Searched refs:phyclk_khz (Results 1 – 7 of 7) sorted by relevance
223 || req_clocks->phyclk_khz > in dce_get_required_clocks_state()478 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) { in dce12_update_clocks()480 clock_voltage_req.clocks_in_khz = new_clocks->phyclk_khz; in dce12_update_clocks()481 dccg->clks.phyclk_khz = new_clocks->phyclk_khz; in dce12_update_clocks()579 if (new_clocks->phyclk_khz) in dcn1_update_clocks()585 || new_clocks->phyclk_khz > dccg->clks.phyclk_khz in dcn1_update_clocks()590 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) { in dcn1_update_clocks()591 dccg->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn1_update_clocks()
163 req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context); in dce100_set_bandwidth()
210 int phyclk_khz; member
1061 context->bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; in dcn_validate_bandwidth()1298 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz); in dcn_find_dcfclk_suits_all()
1338 clocks.phyclk_khz = link_settings.link_rate * 27000; in enable_link_dp()
2367 context->bw.dcn.clk.phyclk_khz = 0; in dcn10_set_bandwidth()
2571 req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context); in dce110_set_bandwidth()
