Searched refs:phy_ctl (Results 1 – 5 of 5) sorted by relevance
267 u16 phy_ctl = 0; in b43_generate_txhdr() local384 phy_ctl |= B43_TXH_PHY_ENC_OFDM; in b43_generate_txhdr()386 phy_ctl |= B43_TXH_PHY_ENC_CCK; in b43_generate_txhdr()388 phy_ctl |= B43_TXH_PHY_SHORTPRMBL; in b43_generate_txhdr()392 phy_ctl |= B43_TXH_PHY_ANT01AUTO; in b43_generate_txhdr()395 phy_ctl |= B43_TXH_PHY_ANT0; in b43_generate_txhdr()398 phy_ctl |= B43_TXH_PHY_ANT1; in b43_generate_txhdr()401 phy_ctl |= B43_TXH_PHY_ANT2; in b43_generate_txhdr()404 phy_ctl |= B43_TXH_PHY_ANT3; in b43_generate_txhdr()577 txhdr->phy_ctl = cpu_to_le16(phy_ctl); in b43_generate_txhdr()
29 __le16 phy_ctl; /* PHY TX control */ member
202 u16 phy_ctl = 0; in generate_txhdr_fw3() local277 phy_ctl |= B43legacy_TX4_PHY_ENC_OFDM; in generate_txhdr_fw3()279 phy_ctl |= B43legacy_TX4_PHY_SHORTPRMBL; in generate_txhdr_fw3()280 phy_ctl |= B43legacy_TX4_PHY_ANTLAST; in generate_txhdr_fw3()353 txhdr->phy_ctl = cpu_to_le16(phy_ctl); in generate_txhdr_fw3()
154 u32 val, phy_ctl; in pcie_phy_read() local162 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; in pcie_phy_read()163 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); in pcie_phy_read()
