Searched refs:omap_ctrl_readl (Results 1 – 9 of 9) sorted by relevance
152 val = omap_ctrl_readl(offset); in omap_ctrl_readb()162 val = omap_ctrl_readl(offset); in omap_ctrl_readw()167 u32 omap_ctrl_readl(u16 offset) in omap_ctrl_readl() function179 tmp = omap_ctrl_readl(offset); in omap_ctrl_writeb()192 tmp = omap_ctrl_readl(offset); in omap_ctrl_writew()423 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); in omap3_control_save_context()424 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); in omap3_control_save_context()426 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); in omap3_control_save_context()428 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); in omap3_control_save_context()430 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); in omap3_control_save_context()[all …]
75 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()83 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()95 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); in am35x_musb_phy_power()103 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) in am35x_musb_phy_power()116 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); in am35x_musb_phy_power()128 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35x_musb_clear_irq()131 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35x_musb_clear_irq()136 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); in am35x_set_mode()
69 reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); in omap3_gpio126_127_129()74 reg = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); in omap3_gpio126_127_129()84 reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); in hsmmc2_internal_input_clk()199 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_enable_emac_int()203 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ in am35xx_enable_emac_int()210 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_disable_emac_int()213 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ in am35xx_disable_emac_int()225 v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35xx_emac_reset()228 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ in am35xx_emac_reset()
61 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); in omap_type()63 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); in omap_type()65 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); in omap_type()67 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); in omap_type()69 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); in omap_type()71 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); in omap_type()285 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); in omap3xxx_check_features()344 status = omap_ctrl_readl(AM33XX_DEV_FEATURE); in am33xx_check_features()
509 extern u32 omap_ctrl_readl(u16 offset);535 #define omap_ctrl_readl(x) 0 macro
66 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); in sr_set_nvalues()
87 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; in omap2_enter_full_retention()
83 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), in omap3_core_save_context()
654 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); in realtime_counter_init()
