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Searched refs:odm_set_bb_reg (Results 1 – 20 of 20) sorted by relevance

/Linux-v4.19/drivers/staging/rtlwifi/phydm/rtl8822b/
Dphydm_hal_api8822b.c122 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD), in phydm_rfe_8822b()
124 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD), in phydm_rfe_8822b()
126 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57); in phydm_rfe_8822b()
127 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57); in phydm_rfe_8822b()
130 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | in phydm_rfe_8822b()
133 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x2); in phydm_rfe_8822b()
134 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | in phydm_rfe_8822b()
137 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x2); in phydm_rfe_8822b()
143 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf050); in phydm_rfe_8822b()
144 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf050); in phydm_rfe_8822b()
[all …]
Dhalphyrf_8822b.c141 odm_set_bb_reg( in odm_tx_pwr_track_set_pwr8822b()
145 odm_set_bb_reg( in odm_tx_pwr_track_set_pwr8822b()
152 odm_set_bb_reg( in odm_tx_pwr_track_set_pwr8822b()
156 odm_set_bb_reg( in odm_tx_pwr_track_set_pwr8822b()
171 odm_set_bb_reg( in odm_tx_pwr_track_set_pwr8822b()
175 odm_set_bb_reg( in odm_tx_pwr_track_set_pwr8822b()
194 odm_set_bb_reg( in odm_tx_pwr_track_set_pwr8822b()
198 odm_set_bb_reg( in odm_tx_pwr_track_set_pwr8822b()
318 odm_set_bb_reg(dm, 0x4C, (BIT(24) | BIT(23)), 0x2); in phy_set_rf_path_switch_8822b()
319 odm_set_bb_reg(dm, 0x974, 0xff, 0xff); in phy_set_rf_path_switch_8822b()
[all …]
Dphydm_iqk_8822b.c125 odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); in phydm_set_iqk_cfir()
128 odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3); in phydm_set_iqk_cfir()
130 odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1); in phydm_set_iqk_cfir()
132 odm_set_bb_reg(dm, 0x1bd4, in phydm_set_iqk_cfir()
137 odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, in phydm_set_iqk_cfir()
195 odm_set_bb_reg(dm, 0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3); in _iqk_fill_iqk_report_8822b()
249 odm_set_bb_reg(dm, 0x198c, 0x7, 0x7); in _iqk_bb_reset_8822b()
260 odm_set_bb_reg(dm, 0xa04, in _iqk_bb_reset_8822b()
265 odm_set_bb_reg(dm, 0x0, BIT(16), 0x0); in _iqk_bb_reset_8822b()
266 odm_set_bb_reg(dm, 0x0, BIT(16), 0x1); in _iqk_bb_reset_8822b()
[all …]
Dphydm_rtl8822b.c25 odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x1); in phydm_dynamic_switch_htstf_mumimo_8822b()
27 odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0); in phydm_dynamic_switch_htstf_mumimo_8822b()
Dphydm_regconfig8822b.c104 odm_set_bb_reg(dm, addr, bitmask, data); in odm_config_bb_agc_8822b()
143 odm_set_bb_reg(dm, addr, bitmask, data); in odm_config_bb_phy_8822b()
/Linux-v4.19/drivers/staging/rtlwifi/phydm/
Dphydm_ccx.c28 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), in phydm_nhm_setting()
30 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), in phydm_nhm_setting()
34 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, in phydm_nhm_setting()
38 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, in phydm_nhm_setting()
40 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, in phydm_nhm_setting()
42 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, in phydm_nhm_setting()
44 odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, in phydm_nhm_setting()
46 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, in phydm_nhm_setting()
48 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, in phydm_nhm_setting()
50 odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, in phydm_nhm_setting()
[all …]
Dphydm_psd.c28 odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx); in phydm_get_psd_data()
30 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), in phydm_get_psd_data()
33 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), in phydm_get_psd_data()
68 odm_set_bb_reg(dm, 0x520, 0xff0000, 0xff); in phydm_psd_stop_trx()
72 odm_set_bb_reg(dm, 0x808, BIT(28), 0); in phydm_psd_stop_trx()
74 odm_set_bb_reg(dm, 0x838, BIT(1), 1); in phydm_psd_stop_trx()
78 odm_set_bb_reg(dm, 0x800, BIT(24), 0); in phydm_psd_stop_trx()
80 odm_set_bb_reg(dm, 0xC14, MASKDWORD, 0x0); in phydm_psd_stop_trx()
139 odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, in phydm_psd()
141 odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, in phydm_psd()
[all …]
Dphydm_dynamicbbpowersaving.c93 odm_set_bb_reg(dm, 0x874, 0x1C0000, in odm_rf_saving()
95 odm_set_bb_reg(dm, 0xc70, BIT(3), in odm_rf_saving()
97 odm_set_bb_reg(dm, 0x85c, 0xFF000000, in odm_rf_saving()
99 odm_set_bb_reg(dm, 0x874, 0xC000, in odm_rf_saving()
101 odm_set_bb_reg(dm, 0xa74, 0xF000, in odm_rf_saving()
103 odm_set_bb_reg(dm, 0x818, BIT(28), in odm_rf_saving()
105 odm_set_bb_reg(dm, 0x818, BIT(28), in odm_rf_saving()
108 odm_set_bb_reg(dm, 0x874, 0x1CC000, in odm_rf_saving()
110 odm_set_bb_reg(dm, 0xc70, BIT(3), dm_ps_table->regc70); in odm_rf_saving()
111 odm_set_bb_reg(dm, 0x85c, 0xFF000000, in odm_rf_saving()
[all …]
Dphydm_adaptivity.c70 odm_set_bb_reg(dm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff); in phydm_nhm_counter_statistics_init()
72 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, in phydm_nhm_counter_statistics_init()
75 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1); in phydm_nhm_counter_statistics_init()
87 odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff); in phydm_nhm_counter_statistics_init()
89 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, in phydm_nhm_counter_statistics_init()
92 odm_set_bb_reg(dm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1); in phydm_nhm_counter_statistics_init()
129 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); in phydm_nhm_counter_statistics_reset()
130 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); in phydm_nhm_counter_statistics_reset()
132 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); in phydm_nhm_counter_statistics_reset()
133 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); in phydm_nhm_counter_statistics_reset()
[all …]
Dphydm_adc_sampling.c90 odm_set_bb_reg(dm, 0x0140, MASKLWORD, in phydm_la_get_tx_pkt_buf()
108 odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page); in phydm_la_get_tx_pkt_buf()
199 odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/ in phydm_la_mode_set_dma_type()
201 odm_set_bb_reg(dm, odm_adc_trigger_jaguar2, 0xf00, in phydm_la_mode_set_dma_type()
218 odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1); in phydm_adc_smp_start()
248 odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0); in phydm_adc_smp_start()
437 odm_set_bb_reg(dm, 0x8f8, in phydm_la_mode_bb_setting()
442 odm_set_bb_reg(dm, 0x8f8, in phydm_la_mode_bb_setting()
446 odm_set_bb_reg(dm, 0x8f8, in phydm_la_mode_bb_setting()
466 odm_set_bb_reg(dm, 0x198C, BIT(2) | BIT(1) | BIT(0), 7); in phydm_la_mode_bb_setting()
[all …]
Dphydm_antdiv.c53 odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000000); in odm_set_ant_config()
55 odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000280); in odm_set_ant_config()
58 odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0000); in odm_set_ant_config()
60 odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0280); in odm_set_ant_config()
Dphydm_dig.c28 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), in phydm_check_ap_write_dig()
32 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), in phydm_check_ap_write_dig()
36 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), in phydm_check_ap_write_dig()
39 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), in phydm_check_ap_write_dig()
43 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), in phydm_check_ap_write_dig()
46 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), in phydm_check_ap_write_dig()
285 odm_set_bb_reg(dm, 0x8c8, 0xe, i); in phydm_set_big_jump_step()
287 odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); in phydm_set_big_jump_step()
339 odm_set_bb_reg(dm, 0xa0c, 0x00003f00, in odm_write_dig()
352 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), in odm_write_dig()
[all …]
Dphydm_cfotracking.c31 odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x007ff800, in odm_set_crystal_cap()
36 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x7FF80000, in odm_set_crystal_cap()
42 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x00FFF000, in odm_set_crystal_cap()
47 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x07FF8000, in odm_set_crystal_cap()
52 odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); in odm_set_crystal_cap()
53 odm_set_bb_reg(dm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); in odm_set_crystal_cap()
57 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000, in odm_set_crystal_cap()
91 odm_set_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm), in odm_set_atc_status()
147 odm_set_bb_reg(dm, 0x10, 0x40, 0x1); in odm_cfo_tracking_init()
Dhalphyrf_ce.c829 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); in odm_txpowertracking_callback_thermal_meter()
830 odm_set_bb_reg( in odm_txpowertracking_callback_thermal_meter()
834 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); in odm_txpowertracking_callback_thermal_meter()
839 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); in odm_txpowertracking_callback_thermal_meter()
840 odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | in odm_txpowertracking_callback_thermal_meter()
843 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); in odm_txpowertracking_callback_thermal_meter()
845 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); in odm_txpowertracking_callback_thermal_meter()
846 odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | in odm_txpowertracking_callback_thermal_meter()
849 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); in odm_txpowertracking_callback_thermal_meter()
854 odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); in odm_txpowertracking_callback_thermal_meter()
[all …]
Dphydm.c220 odm_set_bb_reg(dm, 0x808, MASKBYTE0, in phydm_config_ofdm_rx_path()
243 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8); in phydm_config_trx_path()
245 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4); in phydm_config_trx_path()
247 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc); in phydm_config_trx_path()
307 odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0xc10a0000); in phydm_init_soft_ml_setting()
1456 odm_set_bb_reg(dm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/ in phydm_set_ext_switch()
1457 odm_set_bb_reg(dm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/ in phydm_set_ext_switch()
1460 odm_set_bb_reg(dm, 0xCB4, (BIT(29) | BIT(28)), 1); in phydm_set_ext_switch()
1465 odm_set_bb_reg(dm, 0xCB4, BIT(29) | BIT(28), 2); in phydm_set_ext_switch()
1480 odm_set_bb_reg(dm, 0xD2C, BIT(28), reg_value); in phydm_csi_mask_enable()
[all …]
Dphydm_noisemonitor.c89 odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1); in odm_inband_noise_monitor_n_series()
97 odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0); in odm_inband_noise_monitor_n_series()
223 odm_set_bb_reg(dm, 0x8B4, BIT(6), 1); in odm_inband_noise_monitor_ac_series()
225 odm_set_bb_reg(dm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/ in odm_inband_noise_monitor_ac_series()
253 odm_set_bb_reg(dm, 0x8B4, BIT(6), 0); in odm_inband_noise_monitor_ac_series()
Dphydm_debug.c139 odm_set_bb_reg(dm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ in phydm_print_csi()
186 odm_set_bb_reg(dm, 0x8fc, MASKDWORD, debug_port); in phydm_set_bb_dbg_port()
189 odm_set_bb_reg(dm, 0x908, MASKDWORD, debug_port); in phydm_set_bb_dbg_port()
244 odm_set_bb_reg(dm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7); in phydm_bb_rx_hang_info()
248 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000); in phydm_bb_rx_hang_info()
261 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007); in phydm_bb_rx_hang_info()
273 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204); in phydm_bb_rx_hang_info()
285 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278); in phydm_bb_rx_hang_info()
297 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290); in phydm_bb_rx_hang_info()
310 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2); in phydm_bb_rx_hang_info()
[all …]
Dphydm_interface.h117 void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
Dphydm_interface.c83 void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask, in odm_set_bb_reg() function
Dphydm_rainfo.c322 odm_set_bb_reg(dm, 0x4cc, MASKBYTE3, (ret_value - 1)); in phydm_init_ra_info()