Searched refs:num_tile_mode_states (Results 1 – 5 of 5) sorted by relevance
397 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v6_0_tiling_mode_table_init() local638 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()825 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()1049 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()1273 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
2229 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init() local2236 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2404 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2596 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2785 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2988 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3190 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3359 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3535 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
1024 const u32 num_tile_mode_states = in gfx_v7_0_tiling_mode_table_init() local1047 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1214 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1397 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1567 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
2333 const u32 num_tile_mode_states = in cik_tiling_mode_table_init() local2359 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2502 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2870 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()3013 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2492 const u32 num_tile_mode_states = in si_tiling_mode_table_init() local2509 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()2723 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()2938 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
