Searched refs:num_rbs (Results 1 – 8 of 8) sorted by relevance
2955 u32 len, num_rbs = 0; in iwl_trans_pcie_dump_data() local3047 num_rbs = in iwl_trans_pcie_dump_data()3050 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; in iwl_trans_pcie_dump_data()3051 len += num_rbs * (sizeof(*data) + in iwl_trans_pcie_dump_data()3110 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); in iwl_trans_pcie_dump_data()
507 config[no_regs++] = adev->gfx.config.num_rbs; in amdgpu_debugfs_gca_config_read()
1465 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v6_0_setup_rb()1473 adev->gfx.config.num_rbs >= num_rb_pipes) in gfx_v6_0_setup_rb()
829 unsigned num_rbs; member
1808 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v7_0_setup_rb()1816 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v7_0_setup_rb()
3764 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v8_0_setup_rb()3772 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v8_0_setup_rb()
1729 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v9_0_setup_rb()
2339 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init() local2652 if (num_rbs == 4) { in cik_tiling_mode_table_init()2732 } else if (num_rbs < 4) { in cik_tiling_mode_table_init()
