| /Linux-v4.19/include/linux/mtd/ |
| D | nand.h | 152 int (*erase)(struct nand_device *nand, const struct nand_pos *pos);
153 int (*markbad)(struct nand_device *nand, const struct nand_pos *pos);
154 bool (*isbad)(struct nand_device *nand, const struct nand_pos *pos);
220 static inline struct mtd_info *nanddev_to_mtd(struct nand_device *nand) in nanddev_to_mtd() argument
222 return &nand->mtd; in nanddev_to_mtd()
231 static inline unsigned int nanddev_bits_per_cell(const struct nand_device *nand) in nanddev_bits_per_cell() argument
233 return nand->memorg.bits_per_cell; in nanddev_bits_per_cell()
242 static inline size_t nanddev_page_size(const struct nand_device *nand) in nanddev_page_size() argument
244 return nand->memorg.pagesize; in nanddev_page_size()
254 nanddev_per_page_oobsize(const struct nand_device *nand) in nanddev_per_page_oobsize() argument
[all …]
|
| /Linux-v4.19/drivers/mtd/nand/ |
| D | core.c | 22 bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_isbad() argument
24 if (nanddev_bbt_is_initialized(nand)) { in nanddev_isbad()
28 entry = nanddev_bbt_pos_to_entry(nand, pos); in nanddev_isbad()
29 status = nanddev_bbt_get_block_status(nand, entry); in nanddev_isbad()
32 if (nand->ops->isbad(nand, pos)) in nanddev_isbad()
37 nanddev_bbt_set_block_status(nand, entry, status); in nanddev_isbad()
47 return nand->ops->isbad(nand, pos); in nanddev_isbad()
61 int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_markbad() argument
63 struct mtd_info *mtd = nanddev_to_mtd(nand); in nanddev_markbad()
67 if (nanddev_isbad(nand, pos)) in nanddev_markbad()
[all …]
|
| D | bbt.c | 23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
30 nand->bbt.cache = kzalloc(nwords, GFP_KERNEL); in nanddev_bbt_init()
31 if (!nand->bbt.cache) in nanddev_bbt_init()
44 void nanddev_bbt_cleanup(struct nand_device *nand) in nanddev_bbt_cleanup() argument
46 kfree(nand->bbt.cache); in nanddev_bbt_cleanup()
59 int nanddev_bbt_update(struct nand_device *nand) in nanddev_bbt_update() argument
73 int nanddev_bbt_get_block_status(const struct nand_device *nand, in nanddev_bbt_get_block_status() argument
77 unsigned long *pos = nand->bbt.cache + in nanddev_bbt_get_block_status()
82 if (entry >= nanddev_neraseblocks(nand)) in nanddev_bbt_get_block_status()
[all …]
|
| /Linux-v4.19/drivers/mtd/nand/raw/ |
| D | jz4740_nand.c | 83 struct jz_nand *nand = mtd_to_jz_nand(mtd); in jz_nand_select_chip() local
88 ctrl = readl(nand->base + JZ_REG_NAND_CTRL); in jz_nand_select_chip()
94 banknr = nand->banks[chipnr] - 1; in jz_nand_select_chip()
95 chip->IO_ADDR_R = nand->bank_base[banknr]; in jz_nand_select_chip()
96 chip->IO_ADDR_W = nand->bank_base[banknr]; in jz_nand_select_chip()
98 writel(ctrl, nand->base + JZ_REG_NAND_CTRL); in jz_nand_select_chip()
100 nand->selected_bank = banknr; in jz_nand_select_chip()
105 struct jz_nand *nand = mtd_to_jz_nand(mtd); in jz_nand_cmd_ctrl() local
108 void __iomem *bank_base = nand->bank_base[nand->selected_bank]; in jz_nand_cmd_ctrl()
110 BUG_ON(nand->selected_bank < 0); in jz_nand_cmd_ctrl()
[all …]
|
| D | docg4.c | 267 struct nand_chip *nand = mtd_to_nand(mtd); in docg4_read_buf() local
272 p[i] = readw(nand->IO_ADDR_R); in docg4_read_buf()
278 struct nand_chip *nand = mtd_to_nand(mtd); in docg4_write_buf16() local
283 writew(p[i], nand->IO_ADDR_W); in docg4_write_buf16()
319 static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand) in docg4_wait() argument
322 struct docg4_priv *doc = nand_get_controller_data(nand); in docg4_wait()
343 struct nand_chip *nand = mtd_to_nand(mtd); in docg4_select_chip() local
344 struct docg4_priv *doc = nand_get_controller_data(nand); in docg4_select_chip()
362 struct nand_chip *nand = mtd_to_nand(mtd); in reset() local
363 struct docg4_priv *doc = nand_get_controller_data(nand); in reset()
[all …]
|
| D | nuc900_nand.c | 85 struct nuc900_nand *nand = mtd_to_nuc900(mtd); in nuc900_nand_read_byte() local
87 ret = (unsigned char)read_data_reg(nand); in nuc900_nand_read_byte()
96 struct nuc900_nand *nand = mtd_to_nuc900(mtd); in nuc900_nand_read_buf() local
99 buf[i] = (unsigned char)read_data_reg(nand); in nuc900_nand_read_buf()
106 struct nuc900_nand *nand = mtd_to_nuc900(mtd); in nuc900_nand_write_buf() local
109 write_data_reg(nand, buf[i]); in nuc900_nand_write_buf()
112 static int nuc900_check_rb(struct nuc900_nand *nand) in nuc900_check_rb() argument
115 spin_lock(&nand->lock); in nuc900_check_rb()
116 val = __raw_readl(nand->reg + REG_SMISR); in nuc900_check_rb()
118 spin_unlock(&nand->lock); in nuc900_check_rb()
[all …]
|
| D | jz4780_nand.c | 76 struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); in jz4780_nand_select_chip() local
77 struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); in jz4780_nand_select_chip()
92 struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); in jz4780_nand_cmd_ctrl() local
93 struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); in jz4780_nand_cmd_ctrl()
114 struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); in jz4780_nand_dev_ready() local
116 return !gpiod_get_value_cansleep(nand->busy_gpio); in jz4780_nand_dev_ready()
121 struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); in jz4780_nand_ecc_hwctl() local
123 nand->reading = (mode == NAND_ECC_READ); in jz4780_nand_ecc_hwctl()
129 struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); in jz4780_nand_ecc_calculate() local
130 struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); in jz4780_nand_ecc_calculate()
[all …]
|
| D | sunxi_nand.c | 201 struct nand_chip nand; member
214 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand) in to_sunxi_nand() argument
216 return container_of(nand, struct sunxi_nand_chip, nand); in to_sunxi_nand()
347 struct nand_chip *nand = mtd_to_nand(mtd); in sunxi_nfc_dma_op_prepare() local
348 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); in sunxi_nfc_dma_op_prepare()
395 struct nand_chip *nand = mtd_to_nand(mtd); in sunxi_nfc_dma_op_cleanup() local
396 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); in sunxi_nfc_dma_op_cleanup()
405 struct nand_chip *nand = mtd_to_nand(mtd); in sunxi_nfc_dev_ready() local
406 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); in sunxi_nfc_dev_ready()
407 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); in sunxi_nfc_dev_ready()
[all …]
|
| D | mtk_nand.c | 131 struct nand_chip nand; member
181 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand) in to_mtk_nand() argument
183 return container_of(nand, struct mtk_nfc_nand_chip, nand); in to_mtk_nand()
394 struct nand_chip *nand = mtd_to_nand(mtd); in mtk_nfc_select_chip() local
395 struct mtk_nfc *nfc = nand_get_controller_data(nand); in mtk_nfc_select_chip()
396 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand); in mtk_nfc_select_chip()
595 struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip); in mtk_nfc_bad_mark_swap() local
596 u32 bad_pos = nand->bad_mark.pos; in mtk_nfc_bad_mark_swap()
599 bad_pos += nand->bad_mark.sec * mtk_data_len(chip); in mtk_nfc_bad_mark_swap()
601 bad_pos += nand->bad_mark.sec * chip->ecc.size; in mtk_nfc_bad_mark_swap()
[all …]
|
| /Linux-v4.19/Documentation/devicetree/bindings/mtd/ |
| D | denali-nand.txt | 5 "altr,socfpga-denali-nand" - for Altera SOCFPGA
6 "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
7 "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
13 - clock-names: should contain "nand", "nand_x", "ecc"
16 - nand-ecc-step-size: see nand.txt for details. If present, the value must be
17 512 for "altr,socfpga-denali-nand"
18 1024 for "socionext,uniphier-denali-nand-v5a"
19 1024 for "socionext,uniphier-denali-nand-v5b"
20 - nand-ecc-strength: see nand.txt for details. Valid values are:
21 8, 15 for "altr,socfpga-denali-nand"
[all …]
|
| D | marvell-nand.txt | 5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
23 "marvell,armada-8k-nand[-controller]" compatibles).
28 This property is only used with "marvell,pxa3xx-nand[-controller]"
31 This property is only used with "marvell,pxa3xx-nand[-controller]"
39 - nand-rb: see nand.txt (0-1).
[all …]
|
| D | samsung-s3c2410.txt | 5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
9 - #address-cells, #size-cells : see nand.txt
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
14 Child nodes representing the available nand chips.
17 - nand-ecc-mode : see nand.txt
18 - nand-on-flash-bbt : see nand.txt
26 nand-controller@4e000000 {
[all …]
|
| D | nvidia-tegra20-nand.txt | 5 - "nvidia,tegra20-nand"
11 - nand
15 - nand
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
29 - nand-bus-width : See nand.txt
30 - nand-on-flash-bbt: See nand.txt
31 - nand-ecc-strength: integer representing the number of bits to correct
36 - nand-ecc-maximize: See nand.txt
37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
[all …]
|
| D | mxc-nand.txt | 4 - compatible: "fsl,imxXX-nand"
7 - nand-bus-width: see nand.txt
8 - nand-ecc-mode: see nand.txt
9 - nand-on-flash-bbt: see nand.txt
13 nand@d8000000 {
14 compatible = "fsl,imx27-nand";
17 nand-bus-width = <8>;
18 nand-ecc-mode = "hw";
|
| D | vf610-nfc.txt | 10 - #address-cells: shall be set to 1. Encode the nand CS.
23 Children nodes represent the available nand chips. Currently the driver can
28 - nand-bus-width: see nand.txt
29 - nand-ecc-mode: see nand.txt
32 - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt)
33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are
35 - nand-on-flash-bbt: see nand.txt
39 nfc: nand@400e0000 {
50 nand@0 {
53 nand-bus-width = <8>;
[all …]
|
| D | sunxi-nand.txt | 4 - compatible : "allwinner,sun4i-a10-nand".
6 - interrupts : shall define the nand controller interrupt.
7 - #address-cells: shall be set to 1. Encode the nand CS.
9 - clocks : shall reference nand controller clocks.
10 - clock-names : nand controller internal clock names. Shall contain :
12 * "mod" : nand controller clock
19 Children nodes represent the available nand chips.
25 - nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
28 see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
32 nfc: nand@1c03000 {
[all …]
|
| D | hisi504-nand.txt | 10 - nand-bus-width: See nand.txt.
11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
29 nand: nand@4020000 {
33 nand-bus-width = <8>;
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
|
| D | qcom_nandc.txt | 5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
50 - nand-bus-width: see nand.txt
51 - nand-ecc-strength: see nand.txt. If not specified, then ECC strength will
61 nand-controller@1ac00000 {
62 compatible = "qcom,ipq806x-nand";
77 nand@0 {
80 nand-ecc-strength = <4>;
81 nand-bus-width = <8>;
[all …]
|
| D | tango-nand.txt | 5 - compatible: "sigma,smp8758-nand"
14 See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
18 nandc: nand-controller@2c000 {
19 compatible = "sigma,smp8758-nand";
27 nand@0 {
29 nand-ecc-strength = <14>;
30 nand-ecc-step-size = <1024>;
33 nand@1 {
35 nand-ecc-strength = <14>;
36 nand-ecc-step-size = <1024>;
|
| D | brcm,brcmnand.txt | 36 ranges. Should contain "nand" and (optionally)
37 "flash-dma" and/or "nand-cache".
42 May be "nand", if the SoC has the individual NAND
50 - clock-names : "nand" (required for the above clock)
51 - brcm,nand-has-wp : Some versions of this IP include a write-protect
73 * "brcm,nand-bcm63138"
76 - reg-names: (required) "nand-int-base"
78 * "brcm,nand-bcm6368"
79 - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
82 - reg-names: (required) "nand-int-base"
[all …]
|
| D | atmel-nand.txt | 12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
48 Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
97 nand_controller: nand-controller {
98 compatible = "atmel,sama5d3-nand-controller";
106 nand@3 {
124 "atmel,at91rm9200-nand"
[all …]
|
| D | oxnas-nand.txt | 3 Please refer to nand.txt for generic information regarding MTD NAND bindings.
6 - compatible: "oxsemi,ox820-nand"
15 nandc: nand-controller@41000000 {
16 compatible = "oxsemi,ox820-nand";
23 nand@0 {
27 nand-ecc-mode = "soft";
28 nand-ecc-algo = "hamming";
|
| /Linux-v4.19/drivers/mtd/nand/spi/ |
| D | core.c | 26 struct nand_device *nand = spinand_to_nand(spinand); in spinand_cache_op_adjust_colum() local
29 if (nand->memorg.planes_per_lun < 2) in spinand_cache_op_adjust_colum()
33 shift = fls(nand->memorg.pagesize); in spinand_cache_op_adjust_colum()
67 struct nand_device *nand = spinand_to_nand(spinand); in spinand_get_cfg() local
70 spinand->cur_target >= nand->memorg.ntargets)) in spinand_get_cfg()
79 struct nand_device *nand = spinand_to_nand(spinand); in spinand_set_cfg() local
83 spinand->cur_target >= nand->memorg.ntargets)) in spinand_set_cfg()
133 struct nand_device *nand = spinand_to_nand(spinand); in spinand_select_target() local
136 if (WARN_ON(target >= nand->memorg.ntargets)) in spinand_select_target()
142 if (nand->memorg.ntargets == 1) { in spinand_select_target()
[all …]
|
| /Linux-v4.19/drivers/mtd/nand/raw/atmel/ |
| D | nand-controller.c | 203 struct atmel_nand *nand);
205 int (*setup_data_interface)(struct atmel_nand *nand, int csline,
416 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_read_byte() local
418 return ioread8(nand->activecs->io.virt); in atmel_nand_read_byte()
424 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_read_word() local
426 return ioread16(nand->activecs->io.virt); in atmel_nand_read_word()
432 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_write_byte() local
435 iowrite16(byte | (byte << 8), nand->activecs->io.virt); in atmel_nand_write_byte()
437 iowrite8(byte, nand->activecs->io.virt); in atmel_nand_write_byte()
443 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_read_buf() local
[all …]
|
| /Linux-v4.19/Documentation/devicetree/bindings/pinctrl/ |
| D | lantiq,pinctrl-xway.txt | 51 ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
62 ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy,
63 nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6,
83 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
94 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
106 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
120 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
121 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
122 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
|
