1 /****************************************************************************** 2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 3 * 4 * This program is distributed in the hope that it will be useful, but WITHOUT 5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 7 * more details. 8 * 9 * The full GNU General Public License is included in this distribution in the 10 * file called LICENSE. 11 * 12 * Contact Information: 13 * wlanfae <wlanfae@realtek.com> 14 *****************************************************************************/ 15 16 17 #ifndef R8190P_DEF_H 18 #define R8190P_DEF_H 19 20 #include <linux/types.h> 21 22 #define MAX_SILENT_RESET_RX_SLOT_NUM 10 23 24 #define RX_MPDU_QUEUE 0 25 26 enum rtl819x_loopback { 27 RTL819X_NO_LOOPBACK = 0, 28 RTL819X_MAC_LOOPBACK = 1, 29 RTL819X_DMA_LOOPBACK = 2, 30 RTL819X_CCK_LOOPBACK = 3, 31 }; 32 33 #define DESC90_RATE1M 0x00 34 #define DESC90_RATE2M 0x01 35 #define DESC90_RATE5_5M 0x02 36 #define DESC90_RATE11M 0x03 37 #define DESC90_RATE6M 0x04 38 #define DESC90_RATE9M 0x05 39 #define DESC90_RATE12M 0x06 40 #define DESC90_RATE18M 0x07 41 #define DESC90_RATE24M 0x08 42 #define DESC90_RATE36M 0x09 43 #define DESC90_RATE48M 0x0a 44 #define DESC90_RATE54M 0x0b 45 #define DESC90_RATEMCS0 0x00 46 #define DESC90_RATEMCS1 0x01 47 #define DESC90_RATEMCS2 0x02 48 #define DESC90_RATEMCS3 0x03 49 #define DESC90_RATEMCS4 0x04 50 #define DESC90_RATEMCS5 0x05 51 #define DESC90_RATEMCS6 0x06 52 #define DESC90_RATEMCS7 0x07 53 #define DESC90_RATEMCS8 0x08 54 #define DESC90_RATEMCS9 0x09 55 #define DESC90_RATEMCS10 0x0a 56 #define DESC90_RATEMCS11 0x0b 57 #define DESC90_RATEMCS12 0x0c 58 #define DESC90_RATEMCS13 0x0d 59 #define DESC90_RATEMCS14 0x0e 60 #define DESC90_RATEMCS15 0x0f 61 #define DESC90_RATEMCS32 0x20 62 63 #define SHORT_SLOT_TIME 9 64 #define NON_SHORT_SLOT_TIME 20 65 66 #define RX_SMOOTH 20 67 68 #define QSLT_BK 0x1 69 #define QSLT_BE 0x0 70 #define QSLT_VI 0x4 71 #define QSLT_VO 0x6 72 #define QSLT_BEACON 0x10 73 #define QSLT_HIGH 0x11 74 #define QSLT_MGNT 0x12 75 #define QSLT_CMD 0x13 76 77 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007 78 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa 79 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024 80 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007 81 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10 82 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 83 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd 84 85 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 86 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 87 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 88 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 89 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 90 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 91 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 92 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 93 94 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 95 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 96 #define HAL_PRIME_CHNL_OFFSET_UPPER 2 97 98 99 enum version_8190_loopback { 100 VERSION_8190_BD = 0x3, 101 VERSION_8190_BE 102 }; 103 104 #define IC_VersionCut_C 0x2 105 #define IC_VersionCut_D 0x3 106 #define IC_VersionCut_E 0x4 107 108 enum rf_optype { 109 RF_OP_By_SW_3wire = 0, 110 RF_OP_By_FW, 111 RF_OP_MAX 112 }; 113 114 struct bb_reg_definition { 115 u32 rfintfs; 116 u32 rfintfi; 117 u32 rfintfo; 118 u32 rfintfe; 119 u32 rf3wireOffset; 120 u32 rfLSSI_Select; 121 u32 rfTxGainStage; 122 u32 rfHSSIPara1; 123 u32 rfHSSIPara2; 124 u32 rfSwitchControl; 125 u32 rfAGCControl1; 126 u32 rfAGCControl2; 127 u32 rfRxIQImbalance; 128 u32 rfRxAFE; 129 u32 rfTxIQImbalance; 130 u32 rfTxAFE; 131 u32 rfLSSIReadBack; 132 u32 rfLSSIReadBackPi; 133 }; 134 135 struct tx_fwinfo_8190pci { 136 u8 TxRate:7; 137 u8 CtsEnable:1; 138 u8 RtsRate:7; 139 u8 RtsEnable:1; 140 u8 TxHT:1; 141 u8 Short:1; 142 u8 TxBandwidth:1; 143 u8 TxSubCarrier:2; 144 u8 STBC:2; 145 u8 AllowAggregation:1; 146 u8 RtsHT:1; 147 u8 RtsShort:1; 148 u8 RtsBandwidth:1; 149 u8 RtsSubcarrier:2; 150 u8 RtsSTBC:2; 151 u8 EnableCPUDur:1; 152 153 u32 RxMF:2; 154 u32 RxAMD:3; 155 u32 TxPerPktInfoFeedback:1; 156 u32 Reserved1:2; 157 u32 TxAGCOffset:4; 158 u32 TxAGCSign:1; 159 u32 RAW_TXD:1; 160 u32 Retry_Limit:4; 161 u32 Reserved2:1; 162 u32 PacketID:13; 163 164 165 }; 166 167 struct log_int_8190 { 168 u32 nIMR_COMDOK; 169 u32 nIMR_MGNTDOK; 170 u32 nIMR_HIGH; 171 u32 nIMR_VODOK; 172 u32 nIMR_VIDOK; 173 u32 nIMR_BEDOK; 174 u32 nIMR_BKDOK; 175 u32 nIMR_ROK; 176 u32 nIMR_RCOK; 177 u32 nIMR_TBDOK; 178 u32 nIMR_BDOK; 179 u32 nIMR_RXFOVW; 180 }; 181 182 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag { 183 u8 reserved:4; 184 u8 rxsc:2; 185 u8 sgi_en:1; 186 u8 ex_intf_flag:1; 187 }; 188 189 struct phy_sts_ofdm_819xpci { 190 u8 trsw_gain_X[4]; 191 u8 pwdb_all; 192 u8 cfosho_X[4]; 193 u8 cfotail_X[4]; 194 u8 rxevm_X[2]; 195 u8 rxsnr_X[4]; 196 u8 pdsnr_X[2]; 197 u8 csi_current_X[2]; 198 u8 csi_target_X[2]; 199 u8 sigevm; 200 u8 max_ex_pwr; 201 u8 sgi_en; 202 u8 rxsc_sgien_exflg; 203 }; 204 205 struct phy_sts_cck_819xpci { 206 u8 adc_pwdb_X[4]; 207 u8 sq_rpt; 208 u8 cck_agc_rpt; 209 }; 210 211 212 #define PHY_RSSI_SLID_WIN_MAX 100 213 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10 214 215 struct tx_desc { 216 u16 PktSize; 217 u8 Offset; 218 u8 Reserved1:3; 219 u8 CmdInit:1; 220 u8 LastSeg:1; 221 u8 FirstSeg:1; 222 u8 LINIP:1; 223 u8 OWN:1; 224 225 u8 TxFWInfoSize; 226 u8 RATid:3; 227 u8 DISFB:1; 228 u8 USERATE:1; 229 u8 MOREFRAG:1; 230 u8 NoEnc:1; 231 u8 PIFS:1; 232 u8 QueueSelect:5; 233 u8 NoACM:1; 234 u8 Resv:2; 235 u8 SecCAMID:5; 236 u8 SecDescAssign:1; 237 u8 SecType:2; 238 239 u16 TxBufferSize; 240 u8 PktId:7; 241 u8 Resv1:1; 242 u8 Reserved2; 243 244 u32 TxBuffAddr; 245 246 u32 NextDescAddress; 247 248 u32 Reserved5; 249 u32 Reserved6; 250 u32 Reserved7; 251 }; 252 253 254 struct tx_desc_cmd { 255 u16 PktSize; 256 u8 Reserved1; 257 u8 CmdType:3; 258 u8 CmdInit:1; 259 u8 LastSeg:1; 260 u8 FirstSeg:1; 261 u8 LINIP:1; 262 u8 OWN:1; 263 264 u16 ElementReport; 265 u16 Reserved2; 266 267 u16 TxBufferSize; 268 u16 Reserved3; 269 270 u32 TxBuffAddr; 271 u32 NextDescAddress; 272 u32 Reserved4; 273 u32 Reserved5; 274 u32 Reserved6; 275 }; 276 277 struct rx_desc { 278 u16 Length:14; 279 u16 CRC32:1; 280 u16 ICV:1; 281 u8 RxDrvInfoSize; 282 u8 Shift:2; 283 u8 PHYStatus:1; 284 u8 SWDec:1; 285 u8 LastSeg:1; 286 u8 FirstSeg:1; 287 u8 EOR:1; 288 u8 OWN:1; 289 290 u32 Reserved2; 291 292 u32 Reserved3; 293 294 u32 BufferAddress; 295 296 }; 297 298 299 struct rx_fwinfo { 300 u16 Reserved1:12; 301 u16 PartAggr:1; 302 u16 FirstAGGR:1; 303 u16 Reserved2:2; 304 305 u8 RxRate:7; 306 u8 RxHT:1; 307 308 u8 BW:1; 309 u8 SPLCP:1; 310 u8 Reserved3:2; 311 u8 PAM:1; 312 u8 Mcast:1; 313 u8 Bcast:1; 314 u8 Reserved4:1; 315 316 u32 TSFL; 317 318 }; 319 320 #endif 321
