Searched refs:msm_readl (Results 1 – 14 of 14) sorted by relevance
135 return msm_readl(hdmi->mmio + reg); in hdmi_read()140 return msm_readl(hdmi->qfprom_mmio + reg); in hdmi_qfprom_read()186 return msm_readl(phy->mmio + reg); in hdmi_phy_read()
253 return msm_readl(pll->mmio + reg); in pll_read()
101 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
223 return msm_readl(gpu->mmio + (reg << 2)); in gpu_read()252 val = (u64) msm_readl(gpu->mmio + (lo << 2)); in gpu_read64()253 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); in gpu_read64()
397 u32 msm_readl(const void __iomem *addr);
198 u32 msm_readl(const void __iomem *addr) in msm_readl() function
26 #define edp_read(offset) msm_readl((offset))
21 #define dsi_phy_read(offset) msm_readl((offset))
84 return msm_readl(gmu->mmio + (offset << 2)); in gmu_read()
57 return msm_readl(reg); in pll_read()
69 return msm_readl(mdp4_kms->mmio + reg); in mdp4_read()
49 return msm_readl(mdp5_mdss->mmio + reg); in mdss_read()
190 return msm_readl(mdp5_kms->mmio + reg); in mdp5_read()
55 ver = msm_readl(base + REG_DSI_VERSION); in dsi_get_version()73 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); in dsi_get_version()78 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); in dsi_get_version()194 return msm_readl(msm_host->ctrl_base + reg); in dsi_read()
