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Searched refs:mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c51 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_init_gart_pt_regs()
355 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); in gfxhub_v1_0_init()
Dmmhub_v1_0.c61 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v1_0_init_gart_pt_regs()
602 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); in mmhub_v1_0_init()
Damdgpu_amdkfd_gfx_v9.c1050 …WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(… in set_vm_context_page_table_base()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_1_0_offset.h1540 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 macro
Dmmhub_9_3_0_offset.h1556 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 macro
Dmmhub_9_1_offset.h1572 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1418 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 macro
Dgc_9_1_offset.h1462 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 macro
Dgc_9_2_1_offset.h1400 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 macro