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Searched refs:mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h391 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h557 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro