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Searched refs:mmVCE_UENC_CLOCK_GATING (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dvce_v2_0.c157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
160 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_init_cg()
173 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_mc_resume()
319 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
321 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
334 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
337 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
365 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
369 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
Dvce_v3_0.c188 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
191 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_vce_sw_clock_gating()
214 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
216 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_vce_sw_clock_gating()
535 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v3_0_mc_resume()
770 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_clockgating_state()
773 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_clockgating_state()
Dvce_v4_0.c606 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000); in vce_v4_0_mc_resume()
820 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));
823 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);
846 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));
848 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);
911 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING);
914 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data);
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vce/
Dvce_1_0_d.h53 #define mmVCE_UENC_CLOCK_GATING 0x816F macro
Dvce_2_0_d.h51 #define mmVCE_UENC_CLOCK_GATING 0x81ef macro
Dvce_3_0_d.h55 #define mmVCE_UENC_CLOCK_GATING 0x81ef macro
Dvce_4_0_offset.h116 #define mmVCE_UENC_CLOCK_GATING macro