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Searched refs:mmUVD_VCPU_CACHE_SIZE1 (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h92 #define mmUVD_VCPU_CACHE_SIZE1 0x3D39 macro
Duvd_4_2_d.h63 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 macro
Duvd_5_0_d.h69 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 macro
Duvd_6_0_d.h85 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 macro
Duvd_7_0_offset.h182 #define mmUVD_VCPU_CACHE_SIZE1 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h344 #define mmUVD_VCPU_CACHE_SIZE1 macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c564 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v4_2_mc_resume()
Duvd_v5_0.c274 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v5_0_mc_resume()
Duvd_v7_0.c688 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); in uvd_v7_0_mc_resume()
827 …MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE… in uvd_v7_0_sriov_start()
Duvd_v6_0.c610 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v6_0_mc_resume()
Dvcn_v1_0.c304 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE); in vcn_v1_0_mc_resume()