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Searched refs:mmUVD_VCPU_CACHE_SIZE0 (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h91 #define mmUVD_VCPU_CACHE_SIZE0 0x3D37 macro
Duvd_4_2_d.h61 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
Duvd_5_0_d.h67 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
Duvd_6_0_d.h83 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
Duvd_7_0_offset.h178 #define mmUVD_VCPU_CACHE_SIZE0 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h340 #define mmUVD_VCPU_CACHE_SIZE0 macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c559 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v4_2_mc_resume()
Duvd_v5_0.c269 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v5_0_mc_resume()
Duvd_v7_0.c681 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v7_0_mc_resume()
820 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); in uvd_v7_0_sriov_start()
Duvd_v6_0.c605 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v6_0_mc_resume()
Dvcn_v1_0.c297 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v1_0_mc_resume()