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Searched refs:mmUVD_SUVD_CGC_CTRL (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_d.h91 #define mmUVD_SUVD_CGC_CTRL 0x3be6 macro
Duvd_6_0_d.h107 #define mmUVD_SUVD_CGC_CTRL 0x3be6 macro
Duvd_7_0_offset.h68 #define mmUVD_SUVD_CGC_CTRL … macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h136 #define mmUVD_SUVD_CGC_CTRL … macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c662 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
701 WREG32(mmUVD_SUVD_CGC_CTRL, data2); in uvd_v5_0_set_sw_clock_gating()
Dvcn_v1_0.c435 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
446 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
508 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
519 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
Duvd_v6_0.c1320 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1360 WREG32(mmUVD_SUVD_CGC_CTRL, data2); in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1584 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1631 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);