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Searched refs:mmUVD_STATUS (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c218 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini()
268 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
322 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
348 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
393 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop()
436 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
Duvd_v5_0.c215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
366 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
392 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
454 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
Dvcn_v1_0.c218 if (RREG32_SOC15(VCN, 0, mmUVD_STATUS)) in vcn_v1_0_hw_fini()
698 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start()
728 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, in vcn_v1_0_start()
827 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop()
838 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2); in vcn_v1_0_is_idle()
846 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, 0x2, 0x2, ret); in vcn_v1_0_wait_for_idle()
Duvd_v6_0.c552 if (RREG32(mmUVD_STATUS) != 0) in uvd_v6_0_hw_fini()
793 status = RREG32(mmUVD_STATUS); in uvd_v6_0_start()
820 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v6_0_start()
897 WREG32(mmUVD_STATUS, 0); in uvd_v6_0_stop()
1153 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) in uvd_v6_0_check_soft_reset()
Duvd_v7_0.c801 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
887 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
909 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); in uvd_v7_0_sriov_start()
1024 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); in uvd_v7_0_start()
1054 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, in uvd_v7_0_start()
1459 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h84 #define mmUVD_STATUS 0x3DAF macro
Duvd_4_2_d.h76 #define mmUVD_STATUS 0x3daf macro
Duvd_5_0_d.h82 #define mmUVD_STATUS 0x3daf macro
Duvd_6_0_d.h98 #define mmUVD_STATUS 0x3daf macro
Duvd_7_0_offset.h206 #define mmUVD_STATUS … macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h368 #define mmUVD_STATUS … macro