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Searched refs:mmUVD_SOFT_RESET (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c311 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start()
313 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start()
315 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
332 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
335 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
432 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v4_2_stop()
Duvd_v5_0.c319 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v5_0_start()
350 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
360 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v5_0_start()
376 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
379 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
445 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_stop()
Duvd_v7_0.c854 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
874 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
903 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); in uvd_v7_0_sriov_start()
968 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1004 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1017 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); in uvd_v7_0_start()
1034 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), in uvd_v7_0_start()
1038 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, in uvd_v7_0_start()
1131 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, in uvd_v7_0_stop()
Dvcn_v1_0.c644 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, in vcn_v1_0_start()
678 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, in vcn_v1_0_start()
691 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0); in vcn_v1_0_start()
708 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_start()
712 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start()
816 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, in vcn_v1_0_stop()
Duvd_v6_0.c736 WREG32(mmUVD_SOFT_RESET, in uvd_v6_0_start()
776 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_start()
786 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v6_0_start()
888 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_stop()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h83 #define mmUVD_SOFT_RESET 0x3DA0 macro
Duvd_4_2_d.h67 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_5_0_d.h73 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_6_0_d.h89 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_7_0_offset.h190 #define mmUVD_SOFT_RESET … macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h352 #define mmUVD_SOFT_RESET … macro