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Searched refs:mmUVD_RBC_RB_WPTR (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h73 #define mmUVD_RBC_RB_WPTR 0x3DA5 macro
Duvd_4_2_d.h72 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
Duvd_5_0_d.h78 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
Duvd_6_0_d.h94 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
Duvd_7_0_offset.h198 #define mmUVD_RBC_RB_WPTR … macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c76 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v4_2_ring_get_wptr()
90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_ring_set_wptr()
364 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_start()
Duvd_v5_0.c73 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v5_0_ring_get_wptr()
87 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_ring_set_wptr()
421 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_start()
Duvd_v6_0.c111 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v6_0_ring_get_wptr()
142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_ring_set_wptr()
848 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
Dvcn_v1_0.c758 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_start()
894 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); in vcn_v1_0_dec_ring_get_wptr()
908 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_dec_ring_set_wptr()
Duvd_v7_0.c106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); in uvd_v7_0_ring_get_wptr()
140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
1084 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, in uvd_v7_0_start()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h360 #define mmUVD_RBC_RB_WPTR … macro