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Searched refs:mmUVD_MPC_SET_MUXA1 (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h57 #define mmUVD_MPC_SET_MUXA1 0x3D7A macro
Duvd_4_2_d.h55 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_5_0_d.h61 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_6_0_d.h77 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_7_0_offset.h166 #define mmUVD_MPC_SET_MUXA1 … macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h322 #define mmUVD_MPC_SET_MUXA1 … macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c297 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v4_2_start()
Duvd_v5_0.c343 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v5_0_start()
Duvd_v6_0.c769 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v6_0_start()
Dvcn_v1_0.c671 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); in vcn_v1_0_start()
Duvd_v7_0.c997 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v7_0_start()