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Searched refs:mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h47 #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX … macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h69 #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX … macro