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Searched refs:mmUVD_CGC_GATE (Results 1 – 12 of 12) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h35 #define mmUVD_CGC_GATE 0x3D2A macro
Duvd_4_2_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
Duvd_5_0_d.h48 #define mmUVD_CGC_GATE 0x3d2a macro
Duvd_6_0_d.h64 #define mmUVD_CGC_GATE 0x3d2a macro
Duvd_7_0_offset.h144 #define mmUVD_CGC_GATE … macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c616 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
654 WREG32(mmUVD_CGC_GATE, data3); in uvd_v5_0_enable_clock_gating()
709 data = RREG32(mmUVD_CGC_GATE);
740 WREG32(mmUVD_CGC_GATE, data);
Duvd_v6_0.c631 data = RREG32(mmUVD_CGC_GATE);
699 WREG32(mmUVD_CGC_GATE, data);
1265 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1312 WREG32(mmUVD_CGC_GATE, data3); in uvd_v6_0_enable_clock_gating()
1368 data = RREG32(mmUVD_CGC_GATE);
1401 WREG32(mmUVD_CGC_GATE, data);
Duvd_v7_0.c1629 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1638 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1671 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
Duvd_v4_2.c271 WREG32(mmUVD_CGC_GATE, 0); in uvd_v4_2_start()
Dvcn_v1_0.c361 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
382 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
Dsi.c104 mmUVD_CGC_GATE, 0x00000008, 0x00000000,
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h282 #define mmUVD_CGC_GATE … macro