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Searched refs:mmUVD_CGC_CTRL (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c661 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
700 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
755 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
758 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
764 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
767 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
832 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
Duvd_v4_2.c595 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
598 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
604 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
607 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
618 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
634 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
Dvcn_v1_0.c351 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
359 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
384 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
405 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
476 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
483 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
485 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
506 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
Duvd_v6_0.c1319 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1359 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating()
1416 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1419 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1425 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1428 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1498 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
Duvd_v7_0.c841 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
954 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
1582 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1628 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h34 #define mmUVD_CGC_CTRL 0x3D2C macro
Duvd_4_2_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_5_0_d.h50 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_6_0_d.h66 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_7_0_offset.h146 #define mmUVD_CGC_CTRL … macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h286 #define mmUVD_CGC_CTRL … macro