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Searched refs:mmSDMA0_STATUS_REG (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h86 #define mmSDMA0_STATUS_REG macro
Dsdma0_4_0_offset.h88 #define mmSDMA0_STATUS_REG 0x0025 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h169 #define mmSDMA0_STATUS_REG 0x340d macro
Doss_3_0_1_d.h166 #define mmSDMA0_STATUS_REG 0x340d macro
Doss_2_0_d.h232 #define mmSDMA0_STATUS_REG 0x340d macro
Doss_3_0_d.h303 #define mmSDMA0_STATUS_REG 0x340d macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dsdma_v4_0.c1337 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); in sdma_v4_0_is_idle()
1353 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); in sdma_v4_0_wait_for_idle()
1354 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); in sdma_v4_0_wait_for_idle()
Dvi.c481 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
482 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
Dsoc15.c277 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},