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Searched refs:mmSDMA0_CNTL (Results 1 – 10 of 10) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c373 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in cik_ctx_switch_enable()
388 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in cik_ctx_switch_enable()
1137 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1139 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1142 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1144 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1153 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1155 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1158 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1160 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
Dsdma_v4_0.c567 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v4_0_ctx_switch_enable()
578 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v4_0_ctx_switch_enable()
694 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v4_0_gfx_resume()
696 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); in sdma_v4_0_gfx_resume()
758 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_update_power_gating()
762 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_update_power_gating()
765 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_update_power_gating()
768 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_update_power_gating()
783 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_init_power_gating()
786 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_init_power_gating()
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Dsdma_v2_4.c1071 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1073 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1076 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1078 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1087 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1089 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1092 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1094 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
Dsdma_v3_0.c581 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
600 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_ctx_switch_enable()
1407 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1409 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1412 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1414 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1423 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1425 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1428 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1430 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h68 #define mmSDMA0_CNTL … macro
Dsdma0_4_0_offset.h70 #define mmSDMA0_CNTL 0x001c macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h161 #define mmSDMA0_CNTL 0x3404 macro
Doss_3_0_1_d.h158 #define mmSDMA0_CNTL 0x3404 macro
Doss_2_0_d.h223 #define mmSDMA0_CNTL 0x3404 macro
Doss_3_0_d.h295 #define mmSDMA0_CNTL 0x3404 macro