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Searched refs:mmRLC_PG_CNTL (Results 1 – 12 of 12) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c3738 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3744 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3752 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3758 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3765 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
3771 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_cp_pg()
3778 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
3784 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gds_pg()
3861 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3864 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_cgpg()
[all …]
Dgfx_v9_0.c2107 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2112 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2121 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2126 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2135 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_cp_power_gating()
2140 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_cp_power_gating()
2148 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_cg_power_gating()
2153 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_cg_power_gating()
2161 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_pipeline_powergating()
2166 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_pipeline_powergating()
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Dgfx_v6_0.c2710 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_cp_pg()
2716 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_cp_pg()
2820 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_static_mgpg()
2826 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_static_mgpg()
2834 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_dynamic_mgpg()
2840 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_dynamic_mgpg()
Dgfx_v8_0.c4249 WREG32(mmRLC_PG_CNTL, 0); in gfx_v8_0_rlc_resume()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1165 #define mmRLC_PG_CNTL 0x30D7 macro
Dgfx_7_0_d.h1275 #define mmRLC_PG_CNTL 0x3103 macro
Dgfx_7_2_d.h1288 #define mmRLC_PG_CNTL 0x3103 macro
Dgfx_8_0_d.h1386 #define mmRLC_PG_CNTL 0xec43 macro
Dgfx_8_1_d.h1388 #define mmRLC_PG_CNTL 0xec43 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h5975 #define mmRLC_PG_CNTL … macro
Dgc_9_1_offset.h6254 #define mmRLC_PG_CNTL … macro
Dgc_9_2_1_offset.h6230 #define mmRLC_PG_CNTL … macro