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Searched refs:mmRLC_CNTL (Results 1 – 13 of 13) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/powerplay/inc/
Dpolaris10_pwrvirus.h49 { 0x00000000, mmRLC_CNTL },
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2480 tmp = RREG32(mmRLC_CNTL); in gfx_v6_0_update_rlc()
2482 WREG32(mmRLC_CNTL, rlc); in gfx_v6_0_update_rlc()
2489 orig = data = RREG32(mmRLC_CNTL); in gfx_v6_0_halt_rlc()
2493 WREG32(mmRLC_CNTL, data); in gfx_v6_0_halt_rlc()
2503 WREG32(mmRLC_CNTL, 0); in gfx_v6_0_rlc_stop()
2511 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v6_0_rlc_start()
Dgfx_v7_0.c3420 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3422 WREG32(mmRLC_CNTL, rlc); in gfx_v7_0_update_rlc()
3429 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3435 WREG32(mmRLC_CNTL, data); in gfx_v7_0_halt_rlc()
3488 WREG32(mmRLC_CNTL, 0); in gfx_v7_0_rlc_stop()
3504 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v7_0_rlc_start()
Dgfx_v9_0.c3480 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_enter_rlc_safe_mode()
3509 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_exit_rlc_safe_mode()
Dgfx_v8_0.c5824 data = RREG32(mmRLC_CNTL); in iceland_enter_rlc_safe_mode()
5858 data = RREG32(mmRLC_CNTL); in iceland_exit_rlc_safe_mode()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1136 #define mmRLC_CNTL 0x30C0 macro
Dgfx_7_0_d.h1240 #define mmRLC_CNTL 0x30c0 macro
Dgfx_7_2_d.h1253 #define mmRLC_CNTL 0x30c0 macro
Dgfx_8_0_d.h1342 #define mmRLC_CNTL 0xec00 macro
Dgfx_8_1_d.h1345 #define mmRLC_CNTL 0xec00 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h5901 #define mmRLC_CNTL … macro
Dgc_9_1_offset.h6180 #define mmRLC_CNTL … macro
Dgc_9_2_1_offset.h6144 #define mmRLC_CNTL … macro