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Searched refs:mmMC_SEQ_WR_CTL_D1_LP (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h1006 #define mmMC_SEQ_WR_CTL_D1_LP 0x0AA0 macro
Dgmc_7_1_d.h819 #define mmMC_SEQ_WR_CTL_D1_LP 0xaa0 macro
Dgmc_8_1_d.h923 #define mmMC_SEQ_WR_CTL_D1_LP 0xaa0 macro
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/
Diceland_smumgr.c2427 *out_reg = mmMC_SEQ_WR_CTL_D1_LP; in iceland_check_s0_mc_reg_index()
2625 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in iceland_initialize_mc_reg_table()
Dci_smumgr.c2497 *out_reg = mmMC_SEQ_WR_CTL_D1_LP; in ci_check_s0_mc_reg_index()
2695 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
Dtonga_smumgr.c2878 *out_reg = mmMC_SEQ_WR_CTL_D1_LP; in tonga_check_s0_mc_reg_index()
3092 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, in tonga_initialize_mc_reg_table()
Dfiji_smumgr.c2535 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, in fiji_initialize_mc_reg_table()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c4601 *out_reg = mmMC_SEQ_WR_CTL_D1_LP; in ci_check_s0_mc_reg_index()
4799 WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1)); in ci_initialize_mc_reg_table()