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Searched refs:mmMC_SEQ_RAS_TIMING_LP (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h927 #define mmMC_SEQ_RAS_TIMING_LP 0x0A9B macro
Dgmc_7_1_d.h812 #define mmMC_SEQ_RAS_TIMING_LP 0xa9b macro
Dgmc_8_1_d.h916 #define mmMC_SEQ_RAS_TIMING_LP 0xa9b macro
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/
Diceland_smumgr.c2375 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in iceland_check_s0_mc_reg_index()
2611 …cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SE… in iceland_initialize_mc_reg_table()
Dci_smumgr.c2445 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in ci_check_s0_mc_reg_index()
2681 …cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
Dtonga_smumgr.c2826 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in tonga_check_s0_mc_reg_index()
3064 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, in tonga_initialize_mc_reg_table()
Dfiji_smumgr.c2529 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, in fiji_initialize_mc_reg_table()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c4562 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in ci_check_s0_mc_reg_index()
4785 WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING)); in ci_initialize_mc_reg_table()