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Searched refs:mmGDS_VMID0_BASE (Results 1 – 10 of 10) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h2217 #define mmGDS_VMID0_BASE 0x3300 macro
Dgfx_7_2_d.h2239 #define mmGDS_VMID0_BASE 0x3300 macro
Dgfx_8_0_d.h2437 #define mmGDS_VMID0_BASE 0x3300 macro
Dgfx_8_1_d.h2416 #define mmGDS_VMID0_BASE 0x3300 macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c1316 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); in gfx_v9_0_ngg_init()
3422 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, in gfx_v9_0_ring_emit_gds_switch()
Dgfx_v7_0.c93 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
Dgfx_v8_0.c175 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2981 #define mmGDS_VMID0_BASE macro
Dgc_9_1_offset.h3268 #define mmGDS_VMID0_BASE macro
Dgc_9_2_1_offset.h3218 #define mmGDS_VMID0_BASE macro