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Searched refs:mmGB_TILE_MODE0 (Results 1 – 14 of 14) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dcik.c970 {mmGB_TILE_MODE0},
1064 case mmGB_TILE_MODE0: in cik_get_register_value()
1096 idx = (reg_offset - mmGB_TILE_MODE0); in cik_get_register_value()
Dvi.c495 {mmGB_TILE_MODE0},
588 case mmGB_TILE_MODE0: in vi_get_register_value()
620 idx = (reg_offset - mmGB_TILE_MODE0); in vi_get_register_value()
Dsi.c1051 case mmGB_TILE_MODE0: in si_get_register_value()
1083 idx = (reg_offset - mmGB_TILE_MODE0); in si_get_register_value()
Dgfx_v6_0.c639 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
826 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
1050 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
1274 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
Dgfx_v8_0.c2407 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2597 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2786 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2989 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3191 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3362 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3538 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
Dgfx_v7_0.c1215 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
1398 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
1568 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); in gfx_v7_0_tiling_mode_table_init()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h658 #define mmGB_TILE_MODE0 0x2644 macro
Dgfx_7_0_d.h692 #define mmGB_TILE_MODE0 0x2644 macro
Dgfx_7_2_d.h705 #define mmGB_TILE_MODE0 0x2644 macro
Dgfx_8_0_d.h777 #define mmGB_TILE_MODE0 0x2644 macro
Dgfx_8_1_d.h777 #define mmGB_TILE_MODE0 0x2644 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h938 #define mmGB_TILE_MODE0 macro
Dgc_9_1_offset.h912 #define mmGB_TILE_MODE0 macro
Dgc_9_2_1_offset.h878 #define mmGB_TILE_MODE0 macro