Home
last modified time | relevance | path

Searched refs:mmCP_RB_WPTR_POLL_CNTL (Results 1 – 13 of 13) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c81 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
212 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
Dsi.c528 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
627 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
725 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
805 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
885 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
Dgfx_v9_0.c2067 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); in gfx_v9_0_init_gfx_power_gating()
2070 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); in gfx_v9_0_init_gfx_power_gating()
3661 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_3d_clock_gating()
3665 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_3d_clock_gating()
3711 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_coarse_grain_clock_gating()
3715 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
Dgfx_v8_0.c299 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
462 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
563 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
669 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
Dgfx_v7_0.c3986 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
3989 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v7_0_init_gfx_cgpg()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h524 #define mmCP_RB_WPTR_POLL_CNTL 0x21C2 macro
Dgfx_7_0_d.h513 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
Dgfx_7_2_d.h526 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
Dgfx_8_0_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
Dgfx_8_1_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h212 #define mmCP_RB_WPTR_POLL_CNTL … macro
Dgc_9_1_offset.h212 #define mmCP_RB_WPTR_POLL_CNTL … macro
Dgc_9_2_1_offset.h206 #define mmCP_RB_WPTR_POLL_CNTL … macro