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Searched refs:mmCP_MQD_BASE_ADDR (Results 1 – 14 of 14) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/powerplay/inc/
Dpolaris10_pwrvirus.h1505 { 0x54116f00, mmCP_MQD_BASE_ADDR },
1515 { 0x54117300, mmCP_MQD_BASE_ADDR },
1525 { 0x54117700, mmCP_MQD_BASE_ADDR },
1535 { 0x54117b00, mmCP_MQD_BASE_ADDR },
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v8.c345 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) in kgd_hqd_load()
346 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
360 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
412 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) in kgd_hqd_dump()
Damdgpu_amdkfd_gfx_v7.c373 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_load()
374 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
426 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_dump()
Damdgpu_amdkfd_gfx_v9.c431 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load()
515 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_dump()
Dgfx_v7_0.c3032 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v7_0_mqd_commit()
3035 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) in gfx_v7_0_mqd_commit()
3036 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v7_0_mqd_commit()
Dgfx_v8_0.c4868 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v8_0_mqd_commit()
4882 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v8_0_mqd_commit()
4885 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) in gfx_v8_0_mqd_commit()
4886 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v8_0_mqd_commit()
Dgfx_v9_0.c2880 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, in gfx_v9_0_kiq_init_register()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h567 #define mmCP_MQD_BASE_ADDR 0x3245 macro
Dgfx_7_2_d.h580 #define mmCP_MQD_BASE_ADDR 0x3245 macro
Dgfx_8_0_d.h630 #define mmCP_MQD_BASE_ADDR 0x3245 macro
Dgfx_8_1_d.h630 #define mmCP_MQD_BASE_ADDR 0x3245 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2757 #define mmCP_MQD_BASE_ADDR macro
Dgc_9_1_offset.h3042 #define mmCP_MQD_BASE_ADDR macro
Dgc_9_2_1_offset.h2998 #define mmCP_MQD_BASE_ADDR macro