Searched refs:mmCP_MEC_CNTL (Results 1 – 14 of 14) sorted by relevance
| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/inc/ |
| D | polaris10_pwrvirus.h | 52 { 0x50000000, mmCP_MEC_CNTL },
1502 { 0x00000000, mmCP_MEC_CNTL },
1503 { 0x00000000, mmCP_MEC_CNTL },
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| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | smu8_smumgr.c | 193 mmCP_MEC_CNTL); in smu8_load_mec_firmware()
196 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp); in smu8_load_mec_firmware()
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| D | fiji_smumgr.c | 214 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in fiji_start_avfs_btc()
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| D | polaris10_smumgr.c | 109 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
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| /Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_7_0_d.h | 319 #define mmCP_MEC_CNTL 0x208d macro
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| D | gfx_7_2_d.h | 322 #define mmCP_MEC_CNTL 0x208d macro
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| D | gfx_8_0_d.h | 357 #define mmCP_MEC_CNTL 0x208d macro
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| D | gfx_8_1_d.h | 357 #define mmCP_MEC_CNTL 0x208d macro
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| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v7_0.c | 2674 WREG32(mmCP_MEC_CNTL, 0); in gfx_v7_0_cp_compute_enable()
2676 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v7_0_cp_compute_enable()
4755 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
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| D | gfx_v9_0.c | 2542 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v9_0_cp_compute_enable()
2544 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, in gfx_v9_0_cp_compute_enable()
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| D | gfx_v8_0.c | 4533 WREG32(mmCP_MEC_CNTL, 0); in gfx_v8_0_cp_compute_enable()
4535 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
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| /Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 130 #define mmCP_MEC_CNTL … macro
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| D | gc_9_1_offset.h | 130 #define mmCP_MEC_CNTL … macro
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| D | gc_9_2_1_offset.h | 132 #define mmCP_MEC_CNTL … macro
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