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Searched refs:mmCP_HYP_MEC2_UCODE_DATA (Results 1 – 6 of 6) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/powerplay/inc/
Dpolaris10_pwrvirus.h30 #define mmCP_HYP_MEC2_UCODE_DATA 0xf81d macro
158 { 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA },
159 { 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA },
160 { 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA },
161 { 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA },
162 { 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA },
163 { 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA },
164 { 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA },
165 { 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA },
166 { 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA },
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dpsp_v10_0.c361 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); in psp_v10_0_sram_map()
Dpsp_v3_1.c494 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); in psp_v3_1_sram_map()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6691 #define mmCP_HYP_MEC2_UCODE_DATA … macro
Dgc_9_1_offset.h6972 #define mmCP_HYP_MEC2_UCODE_DATA … macro
Dgc_9_2_1_offset.h7000 #define mmCP_HYP_MEC2_UCODE_DATA … macro