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Searched refs:mmCGTS_SM_CTRL_REG (Results 1 – 13 of 13) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c80 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
211 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
Dsi.c527 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
626 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
724 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
804 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
884 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
Dgfx_v8_0.c298 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
461 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
562 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
668 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
706 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
5752 data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_get_clockgating_state()
5924 temp = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_update_medium_grain_clock_gating()
5935 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v8_0_update_medium_grain_clock_gating()
5966 temp = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_update_medium_grain_clock_gating()
5970 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v8_0_update_medium_grain_clock_gating()
Dgfx_v6_0.c2631 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v6_0_enable_mgcg()
2634 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v6_0_enable_mgcg()
2666 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v6_0_enable_mgcg()
2669 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v6_0_enable_mgcg()
Dgfx_v7_0.c3667 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3679 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
3699 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3702 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h298 #define mmCGTS_SM_CTRL_REG 0x2454 macro
Dgfx_7_0_d.h1480 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_7_2_d.h1501 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_8_0_d.h1694 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_8_1_d.h1662 #define mmCGTS_SM_CTRL_REG 0xf000 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6241 #define mmCGTS_SM_CTRL_REG … macro
Dgc_9_1_offset.h6520 #define mmCGTS_SM_CTRL_REG … macro
Dgc_9_2_1_offset.h6532 #define mmCGTS_SM_CTRL_REG … macro