Searched refs:mg_pll_div0 (Results 1 – 4 of 4) sorted by relevance
176 uint32_t mg_pll_div0; member
2787 pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) | in icl_calc_mg_pll_state()2966 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port)); in icl_pll_get_hw_state()3039 I915_WRITE(MG_PLL_DIV0(port), hw_state->mg_pll_div0); in icl_mg_pll_write()3161 hw_state->mg_pll_div0, in icl_dump_hw_state()
3317 pll->state.hw_state.mg_pll_div0); in i915_shared_dplls_info()
11571 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); in intel_pipe_config_compare()
