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Searched refs:mec_int_cntl (Results 1 – 3 of 3) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c4381 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
4414 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
4415 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
4417 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
4420 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
4421 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
4423 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v7_0.c4815 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v7_0_set_compute_eop_interrupt_state() local
4848 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4849 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
4850 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
4853 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4854 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
4855 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6741 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v8_0_set_compute_eop_interrupt_state() local
6774 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6775 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6776 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
6779 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6780 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6781 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()