| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 636 &data->dpm_table.mclk_table, in smu7_reset_dpm_tables()
704 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v0()
706 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
708 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
710 …data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
711 data->dpm_table.mclk_table.count++; in smu7_setup_dpm_tables_v0()
799 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v1()
801 if (i == 0 || data->dpm_table.mclk_table.dpm_levels in smu7_setup_dpm_tables_v1()
802 [data->dpm_table.mclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
804 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v1()
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| D | smu10_hwmgr.c | 802 struct smu10_voltage_dependency_table *mclk_table = in smu10_force_clock_level() local
830 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) in smu10_force_clock_level()
835 mclk_table->entries[low].clk/100); in smu10_force_clock_level()
839 mclk_table->entries[high].clk/100); in smu10_force_clock_level()
853 struct smu10_voltage_dependency_table *mclk_table = in smu10_print_clock_levels() local
884 for (i = 0; i < mclk_table->count; i++) in smu10_print_clock_levels()
887 mclk_table->entries[i].clk / 100, in smu10_print_clock_levels()
888 ((mclk_table->entries[i].clk / 100) in smu10_print_clock_levels()
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| D | vega10_processpptables.c | 540 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
549 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
551 if (!mclk_table) in get_mclk_voltage_dependency_table()
554 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
557 mclk_table->entries[i].vddInd = in get_mclk_voltage_dependency_table()
559 mclk_table->entries[i].vddciInd = in get_mclk_voltage_dependency_table()
561 mclk_table->entries[i].mvddInd = in get_mclk_voltage_dependency_table()
563 mclk_table->entries[i].clk = in get_mclk_voltage_dependency_table()
567 *pp_vega10_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
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| D | process_pptables_v1_0.c | 374 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
384 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
386 if (NULL == mclk_table) in get_mclk_voltage_dependency_table()
389 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
394 entries, mclk_table, i); in get_mclk_voltage_dependency_table()
405 *pp_tonga_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
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| D | vega10_hwmgr.c | 639 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = in vega10_patch_voltage_dependency_tables_with_lookup_table() local
666 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
667 voltage_id = mclk_table->entries[entry_id].vddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
668 mclk_table->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
670 voltage_id = mclk_table->entries[entry_id].vddciInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
671 mclk_table->entries[entry_id].vddci = in vega10_patch_voltage_dependency_tables_with_lookup_table()
673 voltage_id = mclk_table->entries[entry_id].mvddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
674 mclk_table->entries[entry_id].mvdd = in vega10_patch_voltage_dependency_tables_with_lookup_table()
3770 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, in vega10_get_uclk_index() argument
3776 if (mclk_table == NULL || mclk_table->count == 0) in vega10_get_uclk_index()
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| D | smu7_hwmgr.h | 105 struct smu7_single_dpm_table mclk_table; member
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| D | vega12_hwmgr.c | 2260 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2265 value = (mclk_table->dpm_levels
2266 [mclk_table->count - 1].value -
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| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | ci_dpm.c | 2692 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2695 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
3479 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3480 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3483 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3489 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3499 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3501 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3503 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3608 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
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| D | ci_dpm.h | 70 struct ci_single_dpm_table mclk_table; member
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| /Linux-v4.19/drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 2554 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2557 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
3334 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3335 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3338 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3346 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3356 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3358 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3360 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3465 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
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| D | ci_dpm.h | 69 struct ci_single_dpm_table mclk_table; member
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| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | vegam_smumgr.c | 1046 for (i = 0; i < dpm_table->mclk_table.count; i++) { in vegam_populate_all_memory_levels()
1047 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1051 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1064 (uint8_t)dpm_table->mclk_table.count; in vegam_populate_all_memory_levels()
1066 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in vegam_populate_all_memory_levels()
1068 for (i = 0; i < dpm_table->mclk_table.count; i++) in vegam_populate_all_memory_levels()
1072 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in vegam_populate_all_memory_levels()
1177 data->dpm_table.mclk_table.dpm_levels[0].value, in vegam_populate_smc_acpi_level()
1297 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in vegam_program_memory_timing_parameters()
1300 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
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| D | iceland_smumgr.c | 1360 for (i = 0; i < dpm_table->mclk_table.count; i++) { in iceland_populate_all_memory_levels()
1361 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1363 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1381 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in iceland_populate_all_memory_levels()
1382 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in iceland_populate_all_memory_levels()
1384 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
1621 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in iceland_program_memory_timing_parameters()
1624 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1666 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in iceland_populate_smc_boot_level()
1760 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in iceland_convert_mc_reg_table_to_smc()
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| D | fiji_smumgr.c | 1247 for (i = 0; i < dpm_table->mclk_table.count; i++) { in fiji_populate_all_memory_levels()
1248 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1252 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1270 (uint8_t)dpm_table->mclk_table.count; in fiji_populate_all_memory_levels()
1272 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in fiji_populate_all_memory_levels()
1274 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in fiji_populate_all_memory_levels()
1387 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1408 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1547 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in fiji_program_memory_timing_parameters()
1550 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
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| D | polaris10_smumgr.c | 1137 for (i = 0; i < dpm_table->mclk_table.count; i++) { in polaris10_populate_all_memory_levels()
1138 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1142 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1144 if (i == dpm_table->mclk_table.count - 1) { in polaris10_populate_all_memory_levels()
1161 (uint8_t)dpm_table->mclk_table.count; in polaris10_populate_all_memory_levels()
1163 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in polaris10_populate_all_memory_levels()
1260 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1369 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in polaris10_program_memory_timing_parameters()
1372 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
1375 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); in polaris10_program_memory_timing_parameters()
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| D | ci_smumgr.c | 1312 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
1313 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1315 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1325 if ((dpm_table->mclk_table.count >= 2) in ci_populate_all_memory_levels()
1335 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
1336 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
1337 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in ci_populate_all_memory_levels()
1657 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in ci_program_memory_timing_parameters()
1660 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1702 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in ci_populate_smc_boot_level()
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| D | tonga_smumgr.c | 1096 for (i = 0; i < dpm_table->mclk_table.count; i++) { in tonga_populate_all_memory_levels()
1097 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1102 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1119 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in tonga_populate_all_memory_levels()
1120 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in tonga_populate_all_memory_levels()
1122 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1487 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in tonga_program_memory_timing_parameters()
1490 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
1534 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in tonga_populate_smc_boot_level()
2129 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in tonga_convert_mc_reg_table_to_smc()
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