Searched refs:max_handles (Results 1 – 12 of 12) sorted by relevance
62 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v4_2_resume()75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()166 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; in radeon_uvd_init()186 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; in radeon_uvd_init()219 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_init()256 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_suspend()331 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_free_handles()516 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()542 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()557 for (i = 0; i < p->rdev->uvd.max_handles; ++i) in radeon_uvd_cs_msg()859 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_count_handles()
125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v2_2_resume()
133 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v1_0_resume()
1677 unsigned max_handles; member
205 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; in amdgpu_uvd_sw_init()226 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()245 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()251 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; in amdgpu_uvd_sw_init()267 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_sw_init()354 for (i = 0; i < adev->uvd.max_handles; ++i) in amdgpu_uvd_suspend()358 if (i == adev->uvd.max_handles) in amdgpu_uvd_suspend()424 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_free_handles()744 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_cs_msg()768 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_cs_msg()[all …]
57 unsigned max_handles; member
568 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v4_2_mc_resume()
278 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v5_0_mc_resume()
614 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v6_0_mc_resume()622 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v6_0_mc_resume()
705 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v7_0_mc_resume()837 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); in uvd_v7_0_sriov_start()
719 handle.uvd_max_handles = adev->uvd.max_handles; in amdgpu_info_ioctl()
